From 58a89537931cd243c6ddbb9ff435bc5862fc64b0 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Tue, 12 Jun 2018 22:58:19 +0200
Subject: Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common
 location"

In the end it does not look like RCBA register offsets are fully
compatible over southbridges.

This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4.

Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f.

Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
---
 src/mainboard/google/stout/romstage.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

(limited to 'src/mainboard/google/stout')

diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 9ad03f7366..36ebcf7d36 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -29,7 +29,6 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
-#include <southbridge/intel/common/rcba.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 #include <arch/cpu.h>
@@ -101,9 +100,9 @@ void mainboard_rcba_config(void)
 	DIR_ROUTE(D20IR, PIRQD, PIRQE, PIRQF, PIRQG);
 
 	/* Enable IOAPIC (generic) */
-	RCBA16(EOIC) = 0x0100;
+	RCBA16(OIC) = 0x0100;
 	/* PCH BWG says to read back the IOAPIC enable register */
-	(void) RCBA16(EOIC);
+	(void) RCBA16(OIC);
 
 	/* Disable unused devices (board specific) */
 	reg32 = RCBA32(FD);
-- 
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