From c33ce3554ddc73635084e6e71b5e4f7dae021926 Mon Sep 17 00:00:00 2001 From: Jinkun Hong Date: Thu, 28 Aug 2014 09:37:22 -0700 Subject: rk3288: add ddr driver Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz. ddr timing config file in src\mainboard\google\veyron\sdram_inf Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz). BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I429eb0b8c365c6285fb6cfef008b41776cc9c2d9 Signed-off-by: Patrick Georgi Original-Commit-Id: 52838c68fe6963285c974af5dc5837e819efc321 Original-Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05 Original-Signed-off-by: jinkun.hong Original-Reviewed-on: https://chromium-review.googlesource.com/209465 Original-Reviewed-by: Julius Werner Original-Commit-Queue: Julius Werner Reviewed-on: http://review.coreboot.org/8865 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/mainboard/google/veyron/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/google/veyron/Makefile.inc') diff --git a/src/mainboard/google/veyron/Makefile.inc b/src/mainboard/google/veyron/Makefile.inc index 50a6ba039b..f249cf95af 100644 --- a/src/mainboard/google/veyron/Makefile.inc +++ b/src/mainboard/google/veyron/Makefile.inc @@ -18,6 +18,7 @@ ## romstage-y += romstage.c +romstage-y += sdram_configs.c ramstage-y += mainboard.c ramstage-y += chromeos.c -- cgit v1.2.3