From 4bd65e1c0cd53802abd3598c03d28b82a11be46d Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Wed, 2 Sep 2015 18:10:14 -0700 Subject: rk3288: Allow board-specific APLL (CPU clock) settings This changes the API to rkclk_configure_cpu() such that we can pass in the desired APLL frequency in each veyron board's bootblock.c. Devices with a constrainted form facter (rialto and possibly mickey) will use this to run firmware at a slower speed to mitigate risk of thermal issues (due to the RK808, not the RK3288). BUG=chrome-os-partner:42054 BRANCH=none TEST=amstan says rialto is noticably cooler (and slower) Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd Signed-off-by: Patrick Georgi Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631 Original-Signed-off-by: David Hendricks Original-Reviewed-on: https://chromium-review.googlesource.com/297190 Original-Reviewed-by: Julius Werner Reviewed-on: http://review.coreboot.org/11582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/veyron_danger/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/veyron_danger') diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c index a4a756d283..50d8ef195e 100644 --- a/src/mainboard/google/veyron_danger/bootblock.c +++ b/src/mainboard/google/veyron_danger/bootblock.c @@ -61,7 +61,7 @@ void bootblock_mainboard_init(void) udelay(175);/* Must wait for voltage to stabilize,2mV/us */ rk808_configure_buck(1, 1400); udelay(100);/* Must wait for voltage to stabilize,2mV/us */ - rkclk_configure_cpu(); + rkclk_configure_cpu(APLL_1800_MHZ); /* i2c1 for tpm */ write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1); -- cgit v1.2.3