From 692a2c008304b76e09d6bb6ead0002ffdb9a624a Mon Sep 17 00:00:00 2001 From: "jinkun.hong" Date: Wed, 7 Jan 2015 08:57:48 +0800 Subject: veyron: Add veyron_rialto board Derived from of veyron_brain with new memory configuration. BUG=chrome-os-partner:35072 TEST=built and boot on rialto-rev0 boards. BRANCH=veyron Change-Id: I2c6f74d231e39de76ef2399fdb20efae977b34fa Signed-off-by: Stefan Reinauer Original-Commit-Id: 17d66e5f58562427badd6973ebb053f58573c040 Original-Change-Id: I8626ff5da8098ca120481b8cda0c6703f806711e Original-Signed-off-by: jinkun.hong Original-Signed-off-by: Hung-Te Lin Original-Reviewed-on: https://chromium-review.googlesource.com/238946 Original-Reviewed-by: Julius Werner Original-Trybot-Ready: Julius Werner Reviewed-on: http://review.coreboot.org/9649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/google/veyron_rialto/mainboard.c | 105 +++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 src/mainboard/google/veyron_rialto/mainboard.c (limited to 'src/mainboard/google/veyron_rialto/mainboard.c') diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c new file mode 100644 index 0000000000..6593c6f721 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board.h" + +static void configure_usb(void) +{ + gpio_output(GPIO(0, B, 3), 1); /* HOST1_PWR_EN */ + gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */ + gpio_output(GPIO(7, C, 5), 1); /* 5V_DRV */ +} + +static void configure_emmc(void) +{ + writel(IOMUX_EMMCDATA, &rk3288_grf->iomux_emmcdata); + writel(IOMUX_EMMCPWREN, &rk3288_grf->iomux_emmcpwren); + writel(IOMUX_EMMCCMD, &rk3288_grf->iomux_emmccmd); + + gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */ +} + +static void configure_codec(void) +{ + writel(IOMUX_I2C2, &rk3288_grf->iomux_i2c2); /* CODEC I2C */ + i2c_init(2, 400*KHz); /* CODEC I2C */ + + writel(IOMUX_I2S, &rk3288_grf->iomux_i2s); + writel(IOMUX_I2SCLK, &rk3288_grf->iomux_i2sclk); + + rk808_configure_ldo(6, 1800); /* VCC18_CODEC */ + + /* AUDIO IO domain 1.8V voltage selection */ + writel(RK_SETBITS(1 << 6), &rk3288_grf->io_vsel); + rkclk_configure_i2s(12288000); +} + +static void mainboard_init(device_t dev) +{ + gpio_output(GPIO_RESET, 0); + + configure_usb(); + configure_emmc(); + configure_codec(); + /* No video. */ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; +} + +void mainboard_power_on_backlight(void) +{ +} -- cgit v1.2.3