From da459c46bdbb3bb50ef0680d069bf5e47a7d5fad Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 18 Jun 2020 01:34:48 -0700 Subject: mb/google/zork: Update ramstage GPIOs for v3 schematics for trembyle reference This change updates the baseboard GPIO table in ramstage to match v3 version of trembyle reference schematics. All variants using this reference are accordingly updated to configure the GPIOs that changed as part of v3 schematics. BUG=b:157088093, b:154676993, b:157098434 TEST=Compiles Signed-off-by: Martin Roth Signed-off-by: Furquan Shaikh Change-Id: Ib1d6ee2e995c1fca229c20ea63da9a45fb89f64a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251393 Reviewed-by: Aaron Durbin Commit-Queue: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/42724 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/google/zork/variants/ezkinil/gpio.c | 45 ++++++++++++++++++++--- 1 file changed, 40 insertions(+), 5 deletions(-) (limited to 'src/mainboard/google/zork/variants/ezkinil/gpio.c') diff --git a/src/mainboard/google/zork/variants/ezkinil/gpio.c b/src/mainboard/google/zork/variants/ezkinil/gpio.c index 1b1ed54447..2d6ebe7333 100644 --- a/src/mainboard/google/zork/variants/ezkinil/gpio.c +++ b/src/mainboard/google/zork/variants/ezkinil/gpio.c @@ -6,12 +6,44 @@ #include #include #include -static const struct soc_amd_gpio ezkinil_v1_gpio_set_stage_ram[] = { + +static const struct soc_amd_gpio ezkinil_bid1_gpio_set_stage_ram[] = { + /* DMIC_SEL */ + PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic /* USB_OC4_L - USB_A1 */ PAD_NF(GPIO_14, USB_OC4_L, PULL_UP), /* USB_OC2_L - USB A0 */ PAD_NF(GPIO_18, USB_OC2_L, PULL_UP), + /* EN_PWR_TOUCHPAD_PS2 */ + PAD_GPO(GPIO_67, HIGH), + /* MST_GPIO_2 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_86, PULL_NONE), + /* MST_GPIO_3 (Fw Update HDMI hub) */ + PAD_GPI(GPIO_90, PULL_NONE), +}; + +static const struct soc_amd_gpio ezkinil_bid2_gpio_set_stage_ram[] = { + /* FPMCU_RST_L Change NC */ + PAD_GPI(GPIO_11, PULL_UP), + /* DMIC_SEL */ + PAD_GPO(GPIO_13, LOW), // Select Camera 1 Dmic + /* EN_PWR_TOUCHPAD_PS2 */ + PAD_GPO(GPIO_67, HIGH), + /* FPMCU_BOOT0 Change NC */ + PAD_GPI(GPIO_69, PULL_UP), + /* MST_GPIO_2 (Fw Update HDMI hub) Change NC */ + PAD_GPI(GPIO_86, PULL_UP), }; + +static const struct soc_amd_gpio ezkinil_bid3_gpio_set_stage_ram[] = { + /* FPMCU_RST_L Change NC */ + PAD_GPI(GPIO_11, PULL_UP), + /* FPMCU_BOOT0 Change NC */ + PAD_GPI(GPIO_69, PULL_UP), + /* MST_GPIO_2 (Fw Update HDMI hub) Change NC */ + PAD_GPI(GPIO_86, PULL_UP), +}; + const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) { uint32_t board_version; @@ -25,10 +57,13 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) board_version = 1; if (board_version <= 1) { - *size = ARRAY_SIZE(ezkinil_v1_gpio_set_stage_ram); - return ezkinil_v1_gpio_set_stage_ram; + *size = ARRAY_SIZE(ezkinil_bid1_gpio_set_stage_ram); + return ezkinil_bid1_gpio_set_stage_ram; + } else if (board_version == 2) { + *size = ARRAY_SIZE(ezkinil_bid2_gpio_set_stage_ram); + return ezkinil_bid2_gpio_set_stage_ram; } - *size = 0; - return NULL; + *size = ARRAY_SIZE(ezkinil_bid3_gpio_set_stage_ram); + return ezkinil_bid3_gpio_set_stage_ram; } -- cgit v1.2.3