From 24e62217060b56e75cea67d17d251180eb0ad447 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Mon, 29 Jun 2020 21:31:33 +0800 Subject: mb/google/zork: update G2 TS RST delay time in some m/b+BOE panel(G2 TS), G2 TS may still have chance to lost even rst delay time already meets spec definition: 10us (minimum). Restore G2 TS RST delay time to 50ms, we could have G2 TS working fine on those specific m/b+BOE(G2 TS) panel. BUG=b:159510906 BRANCH=master TEST=emerge-zork coreboot boot with G2 TS, make sure G2 TS is functional Change-Id: Ic629c6c61572ab564def8893ce8d78dfb37d4590 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/42867 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/mainboard/google/zork/variants/berknip/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/google/zork') diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 18288ec203..229469eda7 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -93,7 +93,7 @@ chip soc/amd/picasso register "generic.irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)" - register "generic.reset_delay_ms" = "1" + register "generic.reset_delay_ms" = "50" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 40 on end -- cgit v1.2.3