From 26e8f2fe0125cc6e7727d024bf4bfbd6231c8b27 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Thu, 28 Mar 2013 19:05:29 -0700 Subject: snow: explicitly configure L2 cache This adds a call to explicitly configure L2 cache (though defaults should be set correctly). Change-Id: I120e29c986918c2904a0332e46fcf9f1c5380d85 Signed-off-by: David Hendricks Reviewed-on: http://review.coreboot.org/2950 Reviewed-by: Gabe Black Tested-by: build bot (Jenkins) --- src/mainboard/google/snow/ramstage.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 1751a1b8aa..908162914f 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -45,6 +46,7 @@ void main(void) /* set up dcache and MMU */ /* FIXME: this should happen via resource allocator */ + exynos5250_config_l2_cache(); mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); -- cgit v1.2.3