From 2b28a160618018b4d7b7930362e1088c2313901b Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Tue, 12 Nov 2019 17:21:08 +0100
Subject: sb/intel/bd82x6x: Make the pch_enable_lpc hook optional

This also changes the name to mainboard_pch_lpc_setup to better
reflect that it is an optional mainboard hook.

This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.

Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 src/mainboard/google/butterfly/romstage.c | 2 +-
 src/mainboard/google/link/romstage.c      | 2 +-
 src/mainboard/google/parrot/romstage.c    | 4 ----
 src/mainboard/google/stout/romstage.c     | 2 +-
 4 files changed, 3 insertions(+), 7 deletions(-)

(limited to 'src/mainboard/google')

diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 3aef9d0a09..e1d948d89f 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -28,7 +28,7 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #endif
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* EC Decode Range Port60/64 and Port62/66 */
 	/* Enable EC and PS/2 Keyboard/Mouse*/
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 628e2a0052..3fd90e9b17 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -32,7 +32,7 @@
 
 #include <southbridge/intel/bd82x6x/chip.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
 	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 604cf7b284..caff3f5436 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -26,10 +26,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include "ec/compal/ene932/ec.h"
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_late_rcba_config(void)
 {
 	u32 reg32;
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index cbbae2ee07..d8e04eaa63 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -30,7 +30,7 @@
 #include "ec.h"
 #include "onboard.h"
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/*
 	 * Enable:
-- 
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