From 30f583264d0e9154804cbcdfd8c65518f5e3560f Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 7 Oct 2020 13:27:55 -0500 Subject: mb/google/jecht: Disable PCIe AER Ethernet hardware on jecht variants doesn't support AER, so disable it to mitigate continuous AER timeout errors in dmesg: > pcieport 0000:00:1c.0: AER: Corrected error received: 0000:00:1c.0 > pcieport 0000:00:1c.0: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) > pcieport 0000:00:1c.0: AER: device [8086:9c94] error status/mask=00001000/00002000 > pcieport 0000:00:1c.0: AER: [12] Timeout Change-Id: Ieda82c6e13c2bbc4b3a051a3d2a7ae90728ccdc6 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/46137 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/google/jecht/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 7065081317..4851bd7a68 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -56,4 +56,7 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" +config PCIEXP_AER + def_bool n + endif -- cgit v1.2.3