From 40b7455f9337605b0f3062a6feacb82f43099186 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 10 Dec 2013 09:01:41 -0800 Subject: rambi: limit SD card controller to 2.0 spec MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rambi board can only meet the SD card 2.0 specification. Therefore, the controller capabilities need to be overridden to match. BUG=chrome-os-partner:24423 BRANCH=None TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows high speed as maximum timing as well as 3.3V signal voltage. Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/179415 Reviewed-on: http://review.coreboot.org/4998 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel --- src/mainboard/google/rambi/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 1c24d57d2d..96772ac618 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -27,6 +27,10 @@ chip soc/intel/baytrail register "lpe_codec_clk_freq" = "25" # 25MHz clock register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3