From 579d4550d2ecbd232fb0f14e1c65e741ec572656 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Fri, 16 Mar 2018 12:29:48 -0700 Subject: mb/google/zoombini: Enable NVMe BUG=b:72120814 BRANCH=master TEST=none Change-Id: I64ab38dda78345c1f3d7d3f2bf3cb04c19290ceb Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/25256 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/mainboard/google/zoombini/variants/baseboard/devicetree.cb | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index 44ea0bb5e1..512354ed8f 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -51,6 +51,11 @@ chip soc/intel/cannonlake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + # Enable Root port 8 (PCIe port 9) for NVMe + register "PcieRpEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -81,7 +86,7 @@ chip soc/intel/cannonlake device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.0 on end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 -- cgit v1.2.3