From 72a42886505f54e81f437b618af1ab57e95c4b71 Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Fri, 23 Aug 2013 15:25:07 -0700 Subject: exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420 This changes the number of chip selects that we configure from 2 to 1. On current setups with (x16 memory 4Gbit chips) that means that we're at 2GByte. Technically we should add a second setting in the ares_ddr3_timings and select between the two of the based on board strappings. That would make the CONFIG_RUN_TIME_BANK_NUMBER work properly. I've changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not actually doing the board strapping read right now. This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G systems will no longer put the system in a messed up state (leading to a hang). It also prevents some of the weird boot behavior that we've seen that comes and goes depending on U-Boot alignment. See . This patch was ported from: https://gerrit.chromium.org/gerrit/66117 Signed-off-by: David Hendricks Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d Reviewed-on: https://chromium-review.googlesource.com/167210 Commit-Queue: David Hendricks Tested-by: David Hendricks Reviewed-by: ron minnich (cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880) Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6612 Tested-by: build bot (Jenkins) --- src/mainboard/google/pit/memory.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c index ddd7aa0ff1..4ac3d0c999 100644 --- a/src/mainboard/google/pit/memory.c +++ b/src/mainboard/google/pit/memory.c @@ -86,7 +86,7 @@ const struct mem_timings mem_timings = { DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) | DMC_MEMCONTROL_MEM_TYPE_DDR3 | DMC_MEMCONTROL_MEM_WIDTH_32BIT | - DMC_MEMCONTROL_NUM_CHIP_2 | + DMC_MEMCONTROL_NUM_CHIP_1 | DMC_MEMCONTROL_BL_8 | DMC_MEMCONTROL_PZQ_DISABLE | DMC_MEMCONTROL_MRR_BYTE_7_0, @@ -104,8 +104,8 @@ const struct mem_timings mem_timings = { DMC_CONCONTROL_AREF_EN_DISABLE | DMC_CONCONTROL_IO_PD_CON_DISABLE, .dmc_channels = 1, - .chips_per_channel = 2, - .chips_to_configure = 2, + .chips_per_channel = 1, + .chips_to_configure = 1, .send_zq_init = 1, .gate_leveling_enable = 1, }; -- cgit v1.2.3