From 7439a7adafdf25233701914ebb5e3d8dd7a1756c Mon Sep 17 00:00:00 2001 From: Mac Chiang Date: Fri, 2 Aug 2019 11:09:24 +0800 Subject: mb/google/hatch: Kohaku: Enable DMIC1 in device tree The default is DMIC0 on, but Kohaku is also using DMIC1 BUG=b:133282247 BRANCH=None TEST=arecord -D hw:0,1 -r 48000 -c 4 -f s32 4dmic.wav make sure 4 channels recording work Signed-off-by: Mac Chiang Change-Id: I2dd573e1634516bcf9876bedb92b7d9148bb0e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/34692 Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 3 ++- src/mainboard/google/hatch/variants/kohaku/overridetree.cb | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 00198a5a81..c87a8bcfe7 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -168,11 +168,12 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[3]" = "13" register "PcieClkSrcClkReq[3]" = "3" - #Enable I2S Audio, SSP0, SSP1 and DMIC0 + #Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override) register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkSsp0" = "1" register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "0" # GPIO PM programming register "gpio_override_pm" = "1" diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 13025c83f7..84a90ae68d 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -20,6 +20,9 @@ chip soc/intel/cannonlake # No PCIe WiFi register "PcieRpEnable[13]" = "0" + # Enable DMIC1 + register "PchHdaAudioLinkDmic1" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- cgit v1.2.3