From 98456f4ee6e1d7df2863e2fafe8e505522a48da8 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 8 Nov 2018 15:46:16 -0700 Subject: mb/cannonlake: Remove SmbusEnable from devicetree Remove the SmbusEnable parameter from all Cannon Lake mainboards. Instead this will be determined by the enable state of the SMBUS PCI device. Change-Id: I7ece6768da4c517747af12a07012583575816ae1 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/29551 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/zoombini/variants/baseboard/devicetree.cb | 1 - src/mainboard/google/zoombini/variants/meowth/devicetree.cb | 1 - 2 files changed, 2 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb index c7ef264eaa..36c6595feb 100644 --- a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" # Intel Common SoC Config diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb index c3a546ec2d..b014353e0b 100644 --- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb +++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb @@ -29,7 +29,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" # Intel Common SoC Config -- cgit v1.2.3