From a4faec3b014b54d4619dad31c6d6ede58700d862 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 22 Apr 2020 16:49:28 +0200 Subject: src/mainboard: Const'ify pci_devfn_t devices Change-Id: I5bb1a819475383719dbda32d9b5fea63da1e6713 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40611 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/google/beltino/chromeos.c | 6 +++--- src/mainboard/google/jecht/chromeos.c | 6 +++--- src/mainboard/google/parrot/chromeos.c | 2 +- src/mainboard/google/stout/chromeos.c | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'src/mainboard/google') diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index f3a112d1c7..6c76120813 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -29,20 +29,20 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index b58b35a31f..90284c564f 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -30,20 +30,20 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_write_protect_state(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; } int get_recovery_mode_switch(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; } void init_bootmode_straps(void) { u32 flags = 0; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 818901012b..b1bab25b69 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -15,7 +15,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); struct lb_gpio chromeos_gpios[] = { diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 71d7df5685..03796a6c27 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -60,7 +60,7 @@ int get_recovery_mode_switch(void) if (ec_rec_flag_good) return ec_in_rec_mode; - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3); u8 ec_status = ec_read(EC_STATUS_REG); -- cgit v1.2.3