From 57b2ff886e0ce2c92820f5722c8031def3ac94cf Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sun, 21 Nov 2010 17:29:59 +0000 Subject: Drop excessive whitespace randomly sprinkled in romstage.c files. Also drop some dead or useless code snippets. Abuild-tested. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/hp/dl145_g1/romstage.c | 17 +++-------------- src/mainboard/hp/dl145_g3/romstage.c | 18 +----------------- src/mainboard/hp/dl165_g6_fam10/romstage.c | 15 +-------------- 3 files changed, 5 insertions(+), 45 deletions(-) (limited to 'src/mainboard/hp') diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index f5fdf35eb9..bce716cb1a 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -7,29 +7,23 @@ #include #include #include - #include - #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" - #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" - #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -#include "southbridge/amd/amd8111/amd8111_early_ctrl.c" - static void memreset_setup(void) { if (is_cpu_pre_c0()) { @@ -90,20 +84,15 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" - #include "cpu/amd/dualcore/dualcore.c" #include - -#define RC0 ((1<<1)<<8) // Not sure about these values -#define RC1 ((1<<2)<<8) // Not sure about these values - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/model_fxx/init_cpus.c" - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" +#define RC0 ((1<<1)<<8) // Not sure about these values +#define RC1 ((1<<2)<<8) // Not sure about these values void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 70f829a07f..ce6fd54f8f 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -38,37 +38,27 @@ #include #include #include - #include - #include - #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" - #include "superio/serverengines/pilot/pilot_early_serial.c" #include "superio/serverengines/pilot/pilot_early_init.c" #include "superio/nsc/pc87417/pc87417_early_serial.c" - #include "cpu/x86/bist.h" - #include "northbridge/amd/amdk8/debug.c" - #include "cpu/x86/mtrr/earlymtrr.c" - #include "northbridge/amd/amdk8/setup_resource_map.c" +#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) -#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -93,15 +83,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include - #include "cpu/amd/dualcore/dualcore.c" - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/model_fxx/init_cpus.c" - #include "cpu/amd/model_fxx/fidvid.c" - #include "northbridge/amd/amdk8/early_ht.c" #if 0 @@ -248,4 +233,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } - diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index fbc63e7620..d629a7743d 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -45,29 +45,22 @@ #include "northbridge/amd/amdfam10/amdfam10.h" #include #include - #include "cpu/amd/model_10xxx/apic_timer.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" - #include "superio/serverengines/pilot/pilot_early_serial.c" #include "superio/serverengines/pilot/pilot_early_init.c" #include "superio/nsc/pc87417/pc87417_early_serial.c" - #include "cpu/x86/bist.h" - #include "northbridge/amd/amdfam10/debug.c" - #include "cpu/x86/mtrr/earlymtrr.c" - //#include "northbridge/amd/amdfam10/setup_resource_map.c" +#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) -#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" - static inline void activate_spd_rom(const struct mem_controller *ctrl) { u8 val; @@ -85,18 +78,13 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/amdfam10/amdfam10.h" - #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" - #include "cpu/amd/quadcore/quadcore.c" - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" - #include "northbridge/amd/amdfam10/early_ht.c" static const u8 spd_addr[] = { @@ -113,7 +101,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - u32 bsp_apicid = 0; u32 val; msr_t msr; -- cgit v1.2.3