From d75800c7f2476bee243cc22255acb54d6676d4bc Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 12 May 2014 21:56:27 -0600 Subject: intel/bayleybay: Add Intel's Bayley Bay mainboard MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bay Trail-I Platform – Bayley Bay-I Customer Reference Board The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform. It is designed to support the Bay Trail-I SoC. This implementation uses the Intel FSP (Vist the Intel FSP website for details on FSP architecture and support). This code does not currently support S3. All other features and IO ports are functional. Booted on Ubuntu 14.04, Mint 16, Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and other tests pass. Notes: - Generates a 2MB binary to be flashed to the upper 2MB of the ROM, to preserve the existing Intel Flash Descriptor & TXE binary. - Tested with B0 & B3 Baytrail I parts Board support page will be updated on acceptance. Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600 Signed-off-by: Martin Roth Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/5792 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/intel/Kconfig | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/intel/Kconfig') diff --git a/src/mainboard/intel/Kconfig b/src/mainboard/intel/Kconfig index 75142e39b0..4940c545cf 100644 --- a/src/mainboard/intel/Kconfig +++ b/src/mainboard/intel/Kconfig @@ -3,6 +3,8 @@ if VENDOR_INTEL choice prompt "Mainboard model" +config BOARD_INTEL_BAYLEYBAY_FSP + bool "Bayley Bay FSP-based CRB" config BOARD_INTEL_COUGAR_CANYON2 bool "Cougar Canyon 2 CRB" config BOARD_INTEL_D810E2CB @@ -28,6 +30,7 @@ config BOARD_INTEL_WTM2 endchoice +source "src/mainboard/intel/bayleybay_fsp/Kconfig" source "src/mainboard/intel/cougar_canyon2/Kconfig" source "src/mainboard/intel/d810e2cb/Kconfig" source "src/mainboard/intel/d945gclf/Kconfig" -- cgit v1.2.3