From b4953a93aa855afcf801d6f7d48df18f31ee2598 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 26 May 2018 17:47:42 +0200 Subject: cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/bayleybay_fsp/Kconfig | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mainboard/intel/bayleybay_fsp') diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index e8318cb0f2..7f74342427 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -38,10 +38,6 @@ config MAX_CPUS int default 16 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config FSP_FILE string default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP -- cgit v1.2.3