From c319bab3cd416d85330774f9974b41fcb49075a7 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Sat, 8 Jul 2017 18:16:13 -0700 Subject: intel/cannonlake_rvp: Split RVP boards and SPD Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support. Implement SPD entry to FSPM for both platforms, seperated platform specific DQ/DQS/Rcomp input to FSPM as well. Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/20503 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- .../intel/cannonlake_rvp/spd/Makefile.inc | 28 +++++++ .../intel/cannonlake_rvp/spd/empty.spd.hex | 32 +++++++ .../cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex | 32 +++++++ .../cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex | 32 +++++++ src/mainboard/intel/cannonlake_rvp/spd/spd.h | 28 +++++++ src/mainboard/intel/cannonlake_rvp/spd/spd_util.c | 97 ++++++++++++++++++++++ 6 files changed, 249 insertions(+) create mode 100644 src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc create mode 100644 src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex create mode 100644 src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex create mode 100644 src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex create mode 100644 src/mainboard/intel/cannonlake_rvp/spd/spd.h create mode 100644 src/mainboard/intel/cannonlake_rvp/spd/spd_util.c (limited to 'src/mainboard/intel/cannonlake_rvp/spd') diff --git a/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc new file mode 100644 index 0000000000..052461fc30 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2017 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = empty # 0b000 +SPD_SOURCES += samsung_ddr4_4GB # 1b001 Dual Channel 4GB +SPD_SOURCES += samsung_lpddr4_8GB # 2b001 Dual Channel 8GB +SPD_SOURCES += empty # 3b011 +SPD_SOURCES += empty # 4b100 +SPD_SOURCES += empty # 5b101 +SPD_SOURCES += empty # 6b110 +SPD_SOURCES += empty # 7b111 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex new file mode 100644 index 0000000000..67b46cd239 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex new file mode 100644 index 0000000000..49db2374f4 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 84 19 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E 20 08 +00 05 70 03 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 +16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 64 20 +0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 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00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex b/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex new file mode 100644 index 0000000000..d298629342 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex @@ -0,0 +1,32 @@ +23 10 10 0E 15 19 95 08 00 40 00 00 0A 22 00 00 +48 00 05 FF 92 55 00 00 8C 00 90 A8 90 A0 05 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 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a/src/mainboard/intel/cannonlake_rvp/spd/spd.h b/src/mainboard/intel/cannonlake_rvp/spd/spd.h new file mode 100644 index 0000000000..128eb64a3c --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_ch0(void *dq_map_ptr); +void mainboard_fill_dq_map_ch1(void *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c new file mode 100644 index 0000000000..1e95280d74 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include "spd.h" + +void mainboard_fill_dq_map_ch0(void *dq_map_ptr) +{ + /* DQ byte map Ch0 */ + const u8 dq_map[12] = { + 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00 , + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dq_map_ch1(void *dq_map_ptr) +{ + /* DQ byte map Ch1 */ + const u8 dq_map_u[12] = { + 0x33, 0xCC, 0x33, 0xCC, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + const u8 dq_map_y[12] = { + 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) + memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u)); + else + memcpy(dq_map_ptr, dq_map_y, sizeof(dq_map_y)); +} + +void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map Ch0 */ + const u8 dqs_map_u[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; + + const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) + memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); + else + memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); +} + +void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map Ch1 */ + const u8 dqs_map_u[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; + + const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) + memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); + else + memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 100, 100, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget_U[RCOMP_TARGET_PARAMS] = { + 100, 33, 32, 33, 28 }; + + static const u16 RcompTarget_Y[RCOMP_TARGET_PARAMS] = { + 80, 40, 40, 40, 30 }; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) + memcpy(rcomp_strength_ptr, RcompTarget_U, + sizeof(RcompTarget_U)); + else + memcpy(rcomp_strength_ptr, RcompTarget_Y, + sizeof(RcompTarget_Y)); +} -- cgit v1.2.3