From d07048a7f932aa779dc64d7c503df121c2a76f0b Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Sun, 21 Apr 2019 20:17:11 +0200
Subject: src/mb: Use system_reset()

Use already defined system_reset() function.

Change-Id: I68ff4cffa2bfab6a15299795c3e1837fc9b85806
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 src/mainboard/intel/dcp847ske/early_southbridge.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/mainboard/intel/dcp847ske')

diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 39aeb8f6e2..46f9a94e9e 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -19,6 +19,7 @@
 #include <stdint.h>
 #include <halt.h>
 #include <arch/io.h>
+#include <cf9_reset.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>
@@ -53,8 +54,7 @@ void mainboard_rcba_config(void)
 		RCBA32(BUC) &= ~PCH_DISABLE_GBE;
 		/* Datasheet says clearing the bit requires a reset after */
 		printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n");
-		outb(0xe, 0xcf9);
-		halt();
+		full_reset();
 	}
 #endif
 
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