From fbc508fbb84ddbd047a8fde271c3877f032e48d1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 1 Jun 2017 14:50:07 +0200 Subject: mb/intel/dg41wv: Add mainboard This board was used a test target for the x4x DDR3 raminit patches and has an easy to access DIP8 socket. What is tested and works: * S3 resume * PEG, PCI, USB, SATA * Sound * Ethernet * Native graphic init (textmode and linear fb) on the VGA output * Passing memtest86+ with 2 2Rx8 4G dimms * PS2 Keyboard * Flashing coreboot internally from vendor BIOS. What does not work: * Running dram at 533 MHz (limited at 400MHz currently) Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux 4.10. Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/20003 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/intel/dg41wv/acpi/ec.asl | 1 + src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl | 47 ++++++++++++++++ src/mainboard/intel/dg41wv/acpi/platform.asl | 28 ++++++++++ src/mainboard/intel/dg41wv/acpi/superio.asl | 1 + src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl | 66 +++++++++++++++++++++++ 5 files changed, 143 insertions(+) create mode 100644 src/mainboard/intel/dg41wv/acpi/ec.asl create mode 100644 src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl create mode 100644 src/mainboard/intel/dg41wv/acpi/platform.asl create mode 100644 src/mainboard/intel/dg41wv/acpi/superio.asl create mode 100644 src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl (limited to 'src/mainboard/intel/dg41wv/acpi') diff --git a/src/mainboard/intel/dg41wv/acpi/ec.asl b/src/mainboard/intel/dg41wv/acpi/ec.asl new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/src/mainboard/intel/dg41wv/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000000..18e1f00145 --- /dev/null +++ b/src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + /* PCI1 SLOT 1 */ + Package() { 0x0003ffff, 0, 0, 0x14}, + Package() { 0x0003ffff, 1, 0, 0x15}, + Package() { 0x0003ffff, 2, 0, 0x16}, + Package() { 0x0003ffff, 3, 0, 0x17}, + + /* PCI1 SLOT 2 */ + Package() { 0x0004ffff, 0, 0, 0x15}, + Package() { 0x0004ffff, 1, 0, 0x16}, + Package() { 0x0004ffff, 2, 0, 0x17}, + Package() { 0x0004ffff, 3, 0, 0x14}, + }) +} Else { + Return (Package() { + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} diff --git a/src/mainboard/intel/dg41wv/acpi/platform.asl b/src/mainboard/intel/dg41wv/acpi/platform.asl new file mode 100644 index 0000000000..6c92a4ed47 --- /dev/null +++ b/src/mainboard/intel/dg41wv/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/intel/dg41wv/acpi/superio.asl b/src/mainboard/intel/dg41wv/acpi/superio.asl new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/src/mainboard/intel/dg41wv/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl b/src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl new file mode 100644 index 0000000000..5bec150f0b --- /dev/null +++ b/src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for x4x */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* PEG */ + Package() { 0x0001ffff, 0, 0, 0x10 }, + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 0x10 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 0x10 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 0x10 }, + Package() { 0x001cffff, 1, 0, 0x11 }, + Package() { 0x001cffff, 2, 0, 0x12 }, + Package() { 0x001cffff, 3, 0, 0x13 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 0x17 }, + Package() { 0x001dffff, 1, 0, 0x13 }, + Package() { 0x001dffff, 2, 0, 0x12 }, + Package() { 0x001dffff, 3, 0, 0x10 }, + /* PATA/SATA/SMBUS 0:1f.1-3 */ + Package() { 0x001fffff, 0, 0, 0x12 }, + Package() { 0x001fffff, 1, 0, 0x13 }, + }) + } Else { + Return (Package() { + /* PEG */ + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PATA/SATA/SMBUS 0:1f.1-3 */ + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} -- cgit v1.2.3