From c484da1a98610d783131a3a3998c0a999b97f9f5 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Sat, 9 Nov 2019 14:29:04 +0100
Subject: sb/intel/i82801jx: Add common code for LPC decode

Change-Id: Id706da33f06ceeec39ea50301130770226f0474e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/intel/dg43gt/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/mainboard/intel/dg43gt/devicetree.cb')

diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb
index be0b911a5a..38ae29b031 100644
--- a/src/mainboard/intel/dg43gt/devicetree.cb
+++ b/src/mainboard/intel/dg43gt/devicetree.cb
@@ -42,6 +42,9 @@ chip northbridge/intel/x4x		# Northbridge
 			# Enable PCIe ports 0,2,3 as slots.
 			register "pcie_slot_implemented"	= "0xb"
 
+			register "gen1_dec" = "0x00fc0601"
+			register "gen2_dec" = "0x00fc0291"
+
 			device pci 19.0 on end		# GBE
 			device pci 1a.0 on end		# USB
 			device pci 1a.1 on end		# USB
-- 
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