From f5a57a883b6586c0e6dce9e6e34add09a96e647e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 8 Jan 2019 22:15:53 +0100 Subject: mb: Move timestamp_add_now to northbridge x4x Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/30750 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/dg43gt/romstage.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'src/mainboard/intel/dg43gt') diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index aa8c50ec05..c16160e276 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -23,9 +23,7 @@ #include #include #include -#include #include -#include #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define LPC_DEV PCI_DEV(0, 0x1f, 0) @@ -93,12 +91,7 @@ void mainboard_romstage_entry(unsigned long bist) if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) boot_path = BOOT_PATH_WARM_RESET; - printk(BIOS_DEBUG, "Initializing memory\n"); - timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); - timestamp_add_now(TS_AFTER_INITRAM); - quick_ram_check(); - printk(BIOS_DEBUG, "Memory initialized\n"); x4x_late_init(s3_resume); -- cgit v1.2.3