From d1a1d57adca92dd71f62dfb9363def532c3fc0e6 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Wed, 10 Nov 2010 18:22:11 +0000 Subject: Restructure i3100 Super I/O driver to match the rest of the codebase. - i3100_early_serial.c: - Split out enter/exit functions as the other Super I/Os do. - Make i3100_enable_serial() take a device_t as usual, and convert it to use the standard pnp_* function instead of open-coding the same functionality by hand. - Factor out i3100_configure_uart_clk() from i3100_enable_serial(), we do the same in various other Super I/Os, e.g. ITE ones. - Add some #defines for register / bit values and some comments. - Only functional change: Don't set bit 1 of SIW_CONFIGURATION, it's marked as "READ ONLY, WRITES IGNORED" in the datasheet. Signed-off-by: Uwe Hermann Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/intel/eagleheights/romstage.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/mainboard/intel/eagleheights') diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 8ffe22c168..8e1d212363 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -91,6 +91,8 @@ static inline int spd_read_byte(u16 device, u8 address) #include "northbridge/intel/i3100/reset_test.c" #include "debug.c" +#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) + static void early_config(void) { u32 gcs, rpc, fd; @@ -157,7 +159,9 @@ void main(unsigned long bist) /* Setup the console */ i3100_enable_superio(); - i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE); + i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); + uart_init(); console_init(); -- cgit v1.2.3