From 4041bcf629c9b0239cca7a71091f6e6f0c669b4b Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Sun, 1 Jul 2018 00:31:05 +0530 Subject: mb/intel/icelake_rvp: Add ICL U and Y RVP DIMM configuration List of ICL board variants 1. ICL-U DDR4 - All possible DDR4 memory type LPDDR4 - Memory down fixed DIMM configuration 2. ICL-Y All LPDDR4 DIMM on platform This patch ensures to have all proper SPD configuration. Change-Id: Id596a3c85b13559b3002dcadfee9c945256e28e7 Signed-off-by: Subrata Banik Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/29770 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- src/mainboard/intel/icelake_rvp/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/intel/icelake_rvp/Makefile.inc') diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc index ef0fb34f1b..f63b4bf531 100644 --- a/src/mainboard/intel/icelake_rvp/Makefile.inc +++ b/src/mainboard/intel/icelake_rvp/Makefile.inc @@ -22,9 +22,11 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c +romstage-y += board_id.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-y += board_id.c subdirs-y += variants/baseboard CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include -- cgit v1.2.3