From 07e6499b4813101997f336da9bfce3e02d048de3 Mon Sep 17 00:00:00 2001
From: Aamir Bohra <aamir.bohra@intel.com>
Date: Thu, 22 Nov 2018 17:07:11 +0530
Subject: mb/intel/icelake_rvp: Add EC acpi support code

This implementation adds below changes:

1. Add chrome ec asl support for iclrvp.
2. EC SCI, SMI, S3/S5 wake events.
3. Wake pin and EC SMI GPE confiiguration.

Change-Id: Ie95da92f7125e56fe9ef9d57a1098278c308918e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/29797
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/icelake_rvp/dsdt.asl | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'src/mainboard/intel/icelake_rvp/dsdt.asl')

diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl
index fd8d39494c..c15f80c6a0 100644
--- a/src/mainboard/intel/icelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/icelake_rvp/dsdt.asl
@@ -14,6 +14,9 @@
  */
 
 #include <arch/acpi.h>
+#include "variant/ec.h"
+#include "variant/gpio.h"
+
 DefinitionBlock(
 	"dsdt.aml",
 	"DSDT",
@@ -45,7 +48,21 @@ DefinitionBlock(
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 #endif
 
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+	/* Chrome OS Embedded Controller */
+		Scope (\_SB.PCI0.LPCB)
+		{
+			/* ACPI code for EC SuperIO functions */
+			#include <ec/google/chromeec/acpi/superio.asl>
+			/* ACPI code for EC functions */
+			#include <ec/google/chromeec/acpi/ec.asl>
+		}
+#endif
+
 	// Chipset specific sleep states
 	#include <soc/intel/icelake/acpi/sleepstates.asl>
 
+	// Mainboard specific
+	#include "acpi/mainboard.asl"
+
 }
-- 
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