From 7736bfc443a913a9cde46406bcfc38015ec71f47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 22 Oct 2019 23:05:06 +0200 Subject: soc/intel/sgx: convert SGX and PRMRR devicetree options to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The devicetree is not made for user-choosable options, thus introduce Kconfig options for both SGX and the corresponding PRMRR size. The PRMRR size Kconfig has been implemented as a maximum value. At runtime the final PRMRR size gets selected by checking the supported values in MSR_PRMRR_VALID_CONFIG and trying to select the value nearest to the chosen one. When "Maximum" is chosen, the highest possibly value from the MSR gets used. When a too strict limit is set, coreboot will die, printing an error message. Tested successfully on X11SSM-F Change-Id: I5f08e85898304bba6680075ca5d6bce26aef9a4d Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/35799 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb | 2 -- src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb | 2 -- 2 files changed, 4 deletions(-) (limited to 'src/mainboard/intel/icelake_rvp') diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 6d7fad7623..12accedec4 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -48,8 +48,6 @@ chip soc/intel/icelake register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 4f4130853e..b12c0f7b6c 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -48,8 +48,6 @@ chip soc/intel/icelake register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHda" = "1" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" -- cgit v1.2.3