From e16692ed07ec5a2deaf9769f4ecc3d65dd21ce1d Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 3 Aug 2020 12:54:48 +0200
Subject: mb/**/{devicetree,overridetree}.cb: Indent with tabs

Use tabs instead of eight (sometimes less) spaces.

Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
---
 src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb')

diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 5cfb10da50..9c9a2e767b 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -7,8 +7,8 @@ chip soc/intel/skylake
 	register "gen2_dec" = "0x000c0201"
 
 	# FSP Configuration
-        register "DspEnable" = "1"
-        register "IoBufferOwnership" = "0"
+	register "DspEnable" = "1"
+	register "IoBufferOwnership" = "0"
 	register "HeciEnabled" = "0"
 	register "PmTimerDisabled" = "1"
 	register "Cio2Enable" = "1"
-- 
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