From 1fe32d6bb2579b8c1d14edc31724b758a071d79a Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 10 Apr 2017 21:02:13 -0700 Subject: soc/intel/skylake: Split AC/DC settings for Deep Sx config Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb | 3 ++- src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mainboard/intel/kblrvp/variants') diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb index 00b20ba3f7..23c8d3c962 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb @@ -1,7 +1,8 @@ chip soc/intel/skylake # Enable deep Sx states - register "deep_s5_enable" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb index 369629263b..a56345c00d 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb @@ -7,7 +7,8 @@ chip soc/intel/skylake register "SataPortsEnable[2]" = "1" # Enable deep Sx states - register "deep_s5_enable" = "1" + register "deep_s5_enable_ac" = "1" + register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" # GPE configuration -- cgit v1.2.3