From 7ef19036fbfeaad63ccb4dde26b3133d6128d0b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 8 Oct 2019 00:30:38 +0200 Subject: soc/intel/skylake: move/rename files after drop of FSP 1.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Follow-up commit where only files are moved and paths adapted to make review of the previous commit easier. Change-Id: Iff1acbd286c2ba8e6613e866d4e2f893562e8973 Signed-off-by: Michael Niewöhner Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/35868 Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/intel/kunimitsu/romstage.c | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 src/mainboard/intel/kunimitsu/romstage.c (limited to 'src/mainboard/intel/kunimitsu/romstage.c') diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c new file mode 100644 index 0000000000..e2b065c1cc --- /dev/null +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include "gpio.h" +#include +#include +#include "spd/spd.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, &mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + if (mainboard_has_dual_channel_mem()) + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdDataLen = SPD_LEN; +} -- cgit v1.2.3