From 30eda3edd72f70b3ff7ef46f5cb6e0e346683062 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 16 Nov 2014 20:28:57 -0700 Subject: fsp_baytrail: remove register option for TSEG size Set the UPD entry based on the Kconfig value instead of having two separate places that the value needs to be set. Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/7490 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: FEI WANG --- src/mainboard/intel/minnowmax/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/intel/minnowmax/devicetree.cb') diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index ae11d6a020..72849d6dfd 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -28,7 +28,6 @@ chip soc/intel/fsp_baytrail register "PcdSataMode" = "SATA_MODE_AHCI" register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "PcdMrcInitTsegSize" = "TSEG_SIZE_8_MB" register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" -- cgit v1.2.3