From dcd3d072d4760d9040b61d34c5ee6663a963fb54 Mon Sep 17 00:00:00 2001 From: Srinidhi N Kaushik Date: Thu, 5 Mar 2020 00:41:14 -0800 Subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation This change uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi also export wake gpio for CNVi BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi Signed-off-by: Srinidhi N Kaushik Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39315 Reviewed-by: Wonkyu Kim Reviewed-by: Caveh Jalali Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up3') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 5888db0474..e60e648ef9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -136,7 +136,11 @@ chip soc/intel/tigerlake device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + end + device pci 15.0 on # I2C0 0xA0E8 chip drivers/i2c/max98373 register "vmon_slot_no" = "4" -- cgit v1.2.3