From d72cca0c44bc944fdfbdcbc4b264ba0c3727649b Mon Sep 17 00:00:00 2001 From: Shaunak Saha Date: Wed, 25 Mar 2020 11:42:12 -0700 Subject: mb/tglrvp: Add GPE configuration Update the GPE configuration for dw0, dw1 and dw2. BUG=None TEST=build and boot tglrvp Change-Id: I8b406bcbd710e84cec91a8c2d1557902e929f7cc Signed-off-by: Shaunak Saha Reviewed-on: https://review.coreboot.org/c/coreboot/+/39844 Reviewed-by: Srinidhi N Kaushik Reviewed-by: Caveh Jalali Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/intel/tglrvp/variants/tglrvp_up4') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index f2e5510147..4ff35cc437 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -4,6 +4,14 @@ chip soc/intel/tigerlake device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + # FSP configuration register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" -- cgit v1.2.3