From efcfaa8b6c954fa3b97a9e7a459a1f1cf13c8bc9 Mon Sep 17 00:00:00 2001 From: John Zhao Date: Tue, 28 Jul 2020 11:36:07 -0700 Subject: mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration It is expected both of TCSS D3Hot and D3Cold are enabled by default. BUG=None TEST=Verified both of TCSS D3Hot and D3Cold configuration on TGLRVP. Signed-off-by: John Zhao Change-Id: Id569d8191f82f12379b57a9c50aec31776220bb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44003 Tested-by: build bot (Jenkins) Reviewed-by: Caveh Jalali Reviewed-by: Divya S Sasidharan Reviewed-by: Ravishankar Sarawadi Reviewed-by: Wonkyu Kim --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 4 ---- src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 4 ---- 2 files changed, 8 deletions(-) (limited to 'src/mainboard/intel/tglrvp') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index e8dc7bd8cb..85f9e51084 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -117,10 +117,6 @@ chip soc/intel/tigerlake # Enable S0ix register "s0ix_enable" = "1" - # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" - #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ef8de3cb2d..5c275b3951 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -113,10 +113,6 @@ chip soc/intel/tigerlake # Enable S0ix register "s0ix_enable" = "1" - # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" - #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" -- cgit v1.2.3