From cadc70f7974db25144381b3ea26d4b660233f4dd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 12 May 2019 13:44:22 +0200 Subject: soc/intel/broadwell: Move GPIO init to a common place This also links the gpio configuration instead of including it as a header. Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Matt DeVillier --- src/mainboard/intel/wtm2/Makefile.inc | 2 + src/mainboard/intel/wtm2/gpio.c | 115 ++++++++++++++++++++++++++++++++ src/mainboard/intel/wtm2/gpio.h | 120 ---------------------------------- src/mainboard/intel/wtm2/romstage.c | 4 -- 4 files changed, 117 insertions(+), 124 deletions(-) create mode 100644 src/mainboard/intel/wtm2/gpio.c delete mode 100644 src/mainboard/intel/wtm2/gpio.h (limited to 'src/mainboard/intel/wtm2') diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc index 16137462c9..4c944f2773 100644 --- a/src/mainboard/intel/wtm2/Makefile.inc +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c + romstage-y += chromeos.c ramstage-y += chromeos.c diff --git a/src/mainboard/intel/wtm2/gpio.c b/src/mainboard/intel/wtm2/gpio.c new file mode 100644 index 0000000000..c81ad10081 --- /dev/null +++ b/src/mainboard/intel/wtm2/gpio.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ + PCH_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ + PCH_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ + PCH_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */ + PCH_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */ + PCH_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */ + PCH_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */ + PCH_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */ + PCH_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */ + PCH_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */ + PCH_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */ + PCH_GPIO_UNUSED, /* 11: AMB_THRM_R_N */ + PCH_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */ + PCH_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */ + PCH_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */ + PCH_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */ + PCH_GPIO_OUT_HIGH, /* 16: LAN_RST_N */ + PCH_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */ + PCH_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */ + PCH_GPIO_INPUT, /* 19: EC_IN_RW */ + PCH_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */ + PCH_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */ + PCH_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */ + PCH_GPIO_NATIVE, /* 23: CK_REQ_P5_N */ + PCH_GPIO_OUT_LOW, /* 24: ME_PG_LED */ + PCH_GPIO_INPUT, /* 25: USB_WAKEOUT_N */ + PCH_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */ + PCH_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */ + PCH_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */ + PCH_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */ + PCH_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */ + PCH_GPIO_NATIVE, /* 31: AC_PRESENT_R */ + PCH_GPIO_NATIVE, /* 32: PM_CKRUN_N */ + PCH_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */ + PCH_GPIO_INPUT, /* 34: ESATA_DET_N */ + PCH_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */ + PCH_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */ + PCH_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */ + PCH_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */ + PCH_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */ + PCH_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */ + PCH_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */ + PCH_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */ + PCH_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */ + PCH_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */ + PCH_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */ + PCH_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */ + PCH_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */ + PCH_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */ + PCH_GPIO_INPUT, /* 49: COMBO_JD */ + PCH_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */ + PCH_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */ + PCH_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */ + PCH_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */ + PCH_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */ + PCH_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */ + PCH_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */ + PCH_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */ + PCH_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */ + PCH_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */ + PCH_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */ + PCH_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */ + PCH_GPIO_NATIVE, /* 62: SUS_CK */ + PCH_GPIO_NATIVE, /* 63: SLP_S5_R_N */ + PCH_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */ + PCH_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */ + PCH_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */ + PCH_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */ + PCH_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */ + PCH_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */ + PCH_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */ + PCH_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */ + PCH_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */ + PCH_GPIO_NATIVE, /* 73: PCH_NOT_N */ + PCH_GPIO_NATIVE, /* 74: SML1_DATA */ + PCH_GPIO_NATIVE, /* 75: SML1_CK */ + PCH_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */ + PCH_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */ + PCH_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */ + PCH_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */ + PCH_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */ + PCH_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */ + PCH_GPIO_NATIVE, /* 82: H_RCIN_N */ + PCH_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */ + PCH_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */ + PCH_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */ + PCH_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */ + PCH_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */ + PCH_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */ + PCH_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */ + PCH_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */ + PCH_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */ + PCH_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */ + PCH_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */ + PCH_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ + PCH_GPIO_END +}; diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.h deleted file mode 100644 index 9e6f2e6445..0000000000 --- a/src/mainboard/intel/wtm2/gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef INTEL_WTM2_GPIO_H -#define INTEL_WTM2_GPIO_H - -#include - -static const struct gpio_config mainboard_gpio_config[] = { - PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ - PCH_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ - PCH_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ - PCH_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */ - PCH_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */ - PCH_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */ - PCH_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */ - PCH_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */ - PCH_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */ - PCH_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */ - PCH_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */ - PCH_GPIO_UNUSED, /* 11: AMB_THRM_R_N */ - PCH_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */ - PCH_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */ - PCH_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */ - PCH_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */ - PCH_GPIO_OUT_HIGH, /* 16: LAN_RST_N */ - PCH_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */ - PCH_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */ - PCH_GPIO_INPUT, /* 19: EC_IN_RW */ - PCH_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */ - PCH_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */ - PCH_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */ - PCH_GPIO_NATIVE, /* 23: CK_REQ_P5_N */ - PCH_GPIO_OUT_LOW, /* 24: ME_PG_LED */ - PCH_GPIO_INPUT, /* 25: USB_WAKEOUT_N */ - PCH_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */ - PCH_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */ - PCH_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */ - PCH_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */ - PCH_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */ - PCH_GPIO_NATIVE, /* 31: AC_PRESENT_R */ - PCH_GPIO_NATIVE, /* 32: PM_CKRUN_N */ - PCH_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */ - PCH_GPIO_INPUT, /* 34: ESATA_DET_N */ - PCH_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */ - PCH_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */ - PCH_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */ - PCH_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */ - PCH_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */ - PCH_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */ - PCH_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */ - PCH_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */ - PCH_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */ - PCH_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */ - PCH_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */ - PCH_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */ - PCH_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */ - PCH_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */ - PCH_GPIO_INPUT, /* 49: COMBO_JD */ - PCH_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */ - PCH_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */ - PCH_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */ - PCH_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */ - PCH_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */ - PCH_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */ - PCH_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */ - PCH_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */ - PCH_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */ - PCH_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */ - PCH_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */ - PCH_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */ - PCH_GPIO_NATIVE, /* 62: SUS_CK */ - PCH_GPIO_NATIVE, /* 63: SLP_S5_R_N */ - PCH_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */ - PCH_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */ - PCH_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */ - PCH_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */ - PCH_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */ - PCH_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */ - PCH_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */ - PCH_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */ - PCH_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */ - PCH_GPIO_NATIVE, /* 73: PCH_NOT_N */ - PCH_GPIO_NATIVE, /* 74: SML1_DATA */ - PCH_GPIO_NATIVE, /* 75: SML1_CK */ - PCH_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */ - PCH_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */ - PCH_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */ - PCH_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */ - PCH_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */ - PCH_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */ - PCH_GPIO_NATIVE, /* 82: H_RCIN_N */ - PCH_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */ - PCH_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */ - PCH_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */ - PCH_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */ - PCH_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */ - PCH_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */ - PCH_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */ - PCH_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */ - PCH_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */ - PCH_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */ - PCH_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */ - PCH_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ - PCH_GPIO_END -}; - -#endif diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 3c9bb36363..de4237d222 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -21,7 +21,6 @@ #include #include #include -#include "gpio.h" void mainboard_romstage_entry(struct romstage_params *rp) { @@ -29,9 +28,6 @@ void mainboard_romstage_entry(struct romstage_params *rp) post_code(0x32); - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); -- cgit v1.2.3