From abf2ad716daff751d75907d47bcae4a7044fd7b4 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sun, 7 Feb 2010 21:43:48 +0000 Subject: newconfig is no more. Signed-off-by: Patrick Georgi Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/intel/xe7501devkit/Config.lb | 174 -------------------- src/mainboard/intel/xe7501devkit/Options.lb | 238 ---------------------------- 2 files changed, 412 deletions(-) delete mode 100644 src/mainboard/intel/xe7501devkit/Config.lb delete mode 100644 src/mainboard/intel/xe7501devkit/Options.lb (limited to 'src/mainboard/intel/xe7501devkit') diff --git a/src/mainboard/intel/xe7501devkit/Config.lb b/src/mainboard/intel/xe7501devkit/Config.lb deleted file mode 100644 index 1f0534c8c0..0000000000 --- a/src/mainboard/intel/xe7501devkit/Config.lb +++ /dev/null @@ -1,174 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_GENERATE_ACPI_TABLES object acpi_tables.o end -if CONFIG_HAVE_HARD_RESET object reset.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_HAVE_FALLBACK_BOOT - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit cpu/x86/sse_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/sse_disable.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 - -config chip.h - -# based on sample config for tyan/s2735 -chip northbridge/intel/e7501 - device pci_domain 0 on - device pci 0.0 on end # Chipset host controller - device pci 0.1 on end # Host RASUM controller - device pci 2.0 on # Hub interface B - chip southbridge/intel/i82870 # P64H2 - device pci 1c.0 on end # IOAPIC - bus B - device pci 1d.0 on end # Hub to PCI-B bridge - device pci 1e.0 on end # IOAPIC - bus A - device pci 1f.0 on end # Hub to PCI-A bridge - end - end - device pci 3.0 off end # Hub interface C (82808AA connector - disable for now) - device pci 4.0 on # Hub interface D - chip southbridge/intel/i82870 # P64H2 - device pci 1c.0 on end # IOAPIC - bus B - device pci 1d.0 on end # Hub to PCI-B bridge - device pci 1e.0 on end # IOAPIC - bus A - device pci 1f.0 on end # Hub to PCI-A bridge - end - end - device pci 6.0 on end # E7501 Power management registers? (undocumented) - chip southbridge/intel/i82801ca - device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at) - device pci 1d.1 off end # USB (not populated) - device pci 1d.2 off end # USB (not populated) - device pci 1e.0 on # Hub to PCI bridge - device pci 0.0 on end - end - device pci 1f.0 on # LPC bridge - chip superio/smsc/lpc47b272 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.a off end # ACPI - end - end - device pci 1f.1 on end # IDE - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # AC97 Audio - device pci 1f.6 off end # AC97 Modem - end # SB - end # PCI_DOMAIN - device apic_cluster 0 on - chip cpu/intel/socket_mPGA604 - device apic 0 on end - end - chip cpu/intel/socket_mPGA604 - device apic 6 on end - end - end -end diff --git a/src/mainboard/intel/xe7501devkit/Options.lb b/src/mainboard/intel/xe7501devkit/Options.lb deleted file mode 100644 index 6968f311af..0000000000 --- a/src/mainboard/intel/xe7501devkit/Options.lb +++ /dev/null @@ -1,238 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAX_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_DEBUG -#uses CONFIG_CPU_OPT - -## These are defined in target Config.lb, don't add here -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_FALLBACK_SIZE -uses COREBOOT_EXTRA_VERSION - -## These are defined in mainboard Config.lb, don't add here -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE - -uses CONFIG_HAVE_HARD_RESET - -default CONFIG_HAVE_HARD_RESET = 1 - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=2097152 -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Build code for the fallback boot? -## -default CONFIG_HAVE_FALLBACK_BOOT=1 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - - -## Delay timer options -## -default CONFIG_UDELAY_TSC=1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=12 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## Build code to export ACPI tables? -default CONFIG_GENERATE_ACPI_TABLES=1 - -## -## Build code to export a CMOS option table? -## -default CONFIG_HAVE_OPTION_TABLE=0 - -## CMOS checksum definitions (units == bytes) -## These must match the checksum record in cmos.layout -default CONFIG_LB_CKS_RANGE_START=128 -default CONFIG_LB_CKS_RANGE_END=130 -default CONFIG_LB_CKS_LOC=131 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs, -## so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4. -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 -default CONFIG_LOGICAL_CPUS=0 -default CONFIG_MAX_PHYSICAL_CPUS=2 - -# VGA Console -# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS -# to VGA.rom -default CONFIG_CONSOLE_VGA=0 -default CONFIG_PCI_ROM_RUN=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Motherboard identification -## -default CONFIG_MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT" -default CONFIG_MAINBOARD_VENDOR="Intel" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480 - -### -### coreboot layout values -### - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## CMOS settings not currently supported due to conflicts with factory BIOS -## -default CONFIG_USE_OPTION_TABLE = 0 - -## -## Coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00004000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_DEBUG=1 -# default CONFIG_CPU_OPT="-g" - -### End Options.lb -end -- cgit v1.2.3