From 24d1d4b47274eb82893e6726472a991a36fce0aa Mon Sep 17 00:00:00 2001
From: Stefan Reinauer <reinauer@chromium.org>
Date: Thu, 21 Mar 2013 11:51:41 -0700
Subject: x86: Unify arch/io.h and arch/romcc_io.h

Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.

Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.

Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
---
 src/mainboard/intel/baskingridge/chromeos.c      | 4 ----
 src/mainboard/intel/baskingridge/mainboard_smi.c | 1 -
 src/mainboard/intel/d945gclf/romstage.c          | 1 -
 src/mainboard/intel/d945gclf/smihandler.c        | 1 -
 src/mainboard/intel/eagleheights/romstage.c      | 1 -
 src/mainboard/intel/emeraldlake2/chromeos.c      | 4 ----
 src/mainboard/intel/emeraldlake2/romstage.c      | 1 -
 src/mainboard/intel/emeraldlake2/smihandler.c    | 1 -
 src/mainboard/intel/jarrell/jarrell_fixups.c     | 2 +-
 src/mainboard/intel/jarrell/romstage.c           | 1 -
 src/mainboard/intel/mtarvon/romstage.c           | 1 -
 src/mainboard/intel/truxton/romstage.c           | 1 -
 src/mainboard/intel/wtm1/chromeos.c              | 4 ----
 src/mainboard/intel/wtm1/mainboard_smi.c         | 1 -
 src/mainboard/intel/wtm2/chromeos.c              | 4 ----
 src/mainboard/intel/wtm2/mainboard_smi.c         | 1 -
 src/mainboard/intel/xe7501devkit/romstage.c      | 1 -
 17 files changed, 1 insertion(+), 29 deletions(-)

(limited to 'src/mainboard/intel')

diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 6a1bc26150..9baf3568f7 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -20,12 +20,8 @@
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <arch/io.h>
-#ifdef __PRE_RAM__
-#include <arch/romcc_io.h>
-#else
 #include <device/device.h>
 #include <device/pci.h>
-#endif
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <southbridge/intel/lynxpoint/gpio.h>
 
diff --git a/src/mainboard/intel/baskingridge/mainboard_smi.c b/src/mainboard/intel/baskingridge/mainboard_smi.c
index ecfc3851fb..e543494b25 100644
--- a/src/mainboard/intel/baskingridge/mainboard_smi.c
+++ b/src/mainboard/intel/baskingridge/mainboard_smi.c
@@ -18,7 +18,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <southbridge/intel/lynxpoint/nvs.h>
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index a4cb3b2ac1..a37f605325 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -22,7 +22,6 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
diff --git a/src/mainboard/intel/d945gclf/smihandler.c b/src/mainboard/intel/d945gclf/smihandler.c
index dbd1a81a64..0643ad944f 100644
--- a/src/mainboard/intel/d945gclf/smihandler.c
+++ b/src/mainboard/intel/d945gclf/smihandler.c
@@ -18,7 +18,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include "southbridge/intel/i82801gx/nvs.h"
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 95ad59f9d4..3aeb71c242 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -23,7 +23,6 @@
 #include <delay.h>
 #include <stdint.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index 1c5913a4a2..8e6a732c8e 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -20,12 +20,8 @@
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <arch/io.h>
-#ifdef __PRE_RAM__
-#include <arch/romcc_io.h>
-#else
 #include <device/device.h>
 #include <device/pci.h>
-#endif
 #include <southbridge/intel/bd82x6x/pch.h>
 
 #ifndef __PRE_RAM__
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 4fda2d8252..88bcced67c 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -23,7 +23,6 @@
 #include <lib.h>
 #include <timestamp.h>
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c
index acc1fde93d..ba76eb8bbf 100644
--- a/src/mainboard/intel/emeraldlake2/smihandler.c
+++ b/src/mainboard/intel/emeraldlake2/smihandler.c
@@ -18,7 +18,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <southbridge/intel/bd82x6x/nvs.h>
diff --git a/src/mainboard/intel/jarrell/jarrell_fixups.c b/src/mainboard/intel/jarrell/jarrell_fixups.c
index 1261e61046..9a5774679b 100644
--- a/src/mainboard/intel/jarrell/jarrell_fixups.c
+++ b/src/mainboard/intel/jarrell/jarrell_fixups.c
@@ -1,4 +1,4 @@
-#include <arch/romcc_io.h>
+#include <arch/io.h>
 
 static void mch_reset(void)
 {
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index 784e7df3e6..c6f014c08b 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
 #include <console/console.h>
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index d6bbc5a619..0cab9bdeed 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index d77108f439..71c5f38d8f 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -23,7 +23,6 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <pc80/mc146818rtc.h>
 #include "drivers/pc80/udelay_io.c"
diff --git a/src/mainboard/intel/wtm1/chromeos.c b/src/mainboard/intel/wtm1/chromeos.c
index 1864754e88..8142e6541d 100644
--- a/src/mainboard/intel/wtm1/chromeos.c
+++ b/src/mainboard/intel/wtm1/chromeos.c
@@ -20,12 +20,8 @@
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <arch/io.h>
-#ifdef __PRE_RAM__
-#include <arch/romcc_io.h>
-#else
 #include <device/device.h>
 #include <device/pci.h>
-#endif
 #include <southbridge/intel/lynxpoint/pch.h>
 
 #ifndef __PRE_RAM__
diff --git a/src/mainboard/intel/wtm1/mainboard_smi.c b/src/mainboard/intel/wtm1/mainboard_smi.c
index 281e061687..3ffc68441d 100644
--- a/src/mainboard/intel/wtm1/mainboard_smi.c
+++ b/src/mainboard/intel/wtm1/mainboard_smi.c
@@ -18,7 +18,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <southbridge/intel/lynxpoint/nvs.h>
diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c
index 1864754e88..8142e6541d 100644
--- a/src/mainboard/intel/wtm2/chromeos.c
+++ b/src/mainboard/intel/wtm2/chromeos.c
@@ -20,12 +20,8 @@
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <arch/io.h>
-#ifdef __PRE_RAM__
-#include <arch/romcc_io.h>
-#else
 #include <device/device.h>
 #include <device/pci.h>
-#endif
 #include <southbridge/intel/lynxpoint/pch.h>
 
 #ifndef __PRE_RAM__
diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c
index 281e061687..3ffc68441d 100644
--- a/src/mainboard/intel/wtm2/mainboard_smi.c
+++ b/src/mainboard/intel/wtm2/mainboard_smi.c
@@ -18,7 +18,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/romcc_io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <southbridge/intel/lynxpoint/nvs.h>
diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
index 4e37811b46..342e6f14cb 100644
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ b/src/mainboard/intel/xe7501devkit/romstage.c
@@ -2,7 +2,6 @@
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
-#include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
 #include <stdlib.h>
-- 
cgit v1.2.3