From 2b4ba5105c2e96cb2943436fc41f5624568e1646 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 2 Feb 2019 13:39:56 +0530 Subject: mb/intel/../../cml_u: Override LPSS related FSP UPD for CMLRVP This patch overrides required LPSS FSP UPDs for CMLRVP from devicetree.cb File devicetree-override.cb will override required UPDs and is only applicable to CML soc for now Change-Id: I82e3323df952762e2d9c14f1e3cfa75872ccc9b4 Signed-off-by: Subrata Banik Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/31285 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../intel/coffeelake_rvp/variants/cml_u/devicetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb index e30da3af4d..6484330ae1 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb @@ -8,6 +8,22 @@ chip soc/intel/cannonlake register "SaGv" = "SaGv_Enabled" register "ScsEmmcHs400Enabled" = "1" register "HeciEnabled" = "1" + register "s0ix_enable" = "1" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" -- cgit v1.2.3