From 4d5c4e069cb99e715d04bf238e406a008f16707d Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Wed, 29 Jul 2020 22:28:37 +0200 Subject: soc/intel/skylake: Enable SA IMGU depending on devicetree configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, SA IMGU gets enabled by the option SaImguEnable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SA IMGU controller. All corresponding mainboards were checked if the devicetree configuration matches the SaImguEnable setting, and missing entries were added. Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index ea3d814e20..fe5edbe9b9 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -10,7 +10,6 @@ chip soc/intel/skylake register "DspEnable" = "1" register "PmTimerDisabled" = "1" register "Cio2Enable" = "1" - register "SaImguEnable" = "1" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ @@ -121,6 +120,7 @@ chip soc/intel/skylake }" device domain 0 on + device pci 05.0 on end # SA IMGU device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 -- cgit v1.2.3