From 57c8143350bf357dd7edc13ddf735084eea53d07 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sat, 25 Jul 2020 07:50:51 +0200 Subject: soc/intel/skylake: Enable LAN depending on devicetree configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently LAN gets enabled by the option EnableLan, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement of the LAN controller. I checked all corresponding mainboards if the devicetree configuration matches the EnableLan setting. Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel --- src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb | 2 -- src/mainboard/intel/saddlebrook/devicetree.cb | 2 -- 2 files changed, 4 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b5979fc8a8..a8e51950d8 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -50,8 +50,6 @@ chip soc/intel/skylake # RP17, uses uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" - register EnableLan = "1" - # USB related register "SsicPortEnable" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 71102791a6..5a24705206 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -140,8 +140,6 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[5]" = "0" register "PcieRpClkReqNumber[12]" = "1" - register "EnableLan" = "1" - # USB related register "SsicPortEnable" = "1" -- cgit v1.2.3