From 5a1f5970857a5ad1fda0cf9d5945192408bf537b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 31 Mar 2010 14:34:40 +0000 Subject: This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and makes include/console/console.h and console/console.c usable both in __PRE_RAM__ and coreboot_ram stages. While debugging this, I removed an indirection from the e7520 ram init code (same as we did on a couple of other chipsets, removes some register pressure from romcc) Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code in cache_as_ram.inc) Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before. Signed-off-by: Stefan Reinauer Acked-by: Myles Watson git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/intel/d945gclf/romstage.c | 2 +- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/jarrell/romstage.c | 4 +++- src/mainboard/intel/mtarvon/romstage.c | 2 +- src/mainboard/intel/truxton/romstage.c | 2 +- src/mainboard/intel/xe7501devkit/romstage.c | 2 +- 6 files changed, 8 insertions(+), 6 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 48f3f78e7b..7767b1cc47 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -38,7 +38,7 @@ #include #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include #if CONFIG_USBDEBUG_DIRECT diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 7eb83c9153..13c7e951f3 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include #include "lib/ramtest.c" diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index 04b552fb25..4255e43c21 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -60,10 +60,12 @@ static void main(unsigned long bist) static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 }, .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 }, } diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index f23169736b..ed8e647c53 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -28,7 +28,7 @@ #include #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index b2e04be896..4163c873b0 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -29,7 +29,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "pc80/udelay_io.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 240e917964..685f3b8700 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -9,7 +9,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" -- cgit v1.2.3