From 6d1b0d84f2f35bd2a8db77a16ef54c7cf5c4b838 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 13 Apr 2010 00:02:20 +0000 Subject: Fix eagleheights not a 6ex board, but using the same CAR code. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/intel/eagleheights/romstage.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 13c7e951f3..71bda84c0f 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -163,7 +163,7 @@ void early_config(void) { pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); } -void real_main(unsigned long bist) +void main(unsigned long bist) { /* int boot_mode = 0; */ @@ -232,6 +232,3 @@ void real_main(unsigned long bist) sdram_initialize(ARRAY_SIZE(mch), mch); } -/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */ -#include "cpu/intel/model_6ex/cache_as_ram_disable.c" - -- cgit v1.2.3