From a0a3727dbbd7f3ae9f9021e0797ce2fc61d1b79e Mon Sep 17 00:00:00 2001
From: Aaron Durbin <adurbin@chromium.org>
Date: Thu, 14 Aug 2014 08:35:11 -0500
Subject: intel/cpu: rename car.h to romstage.h

This header has nothing to do with cache-as-ram. Therefore, 'car'
is the wrong term to use. It is about providing a prototype for
*romstage*.

Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6661
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/mainboard/intel/d810e2cb/romstage.c     | 2 +-
 src/mainboard/intel/d945gclf/romstage.c     | 2 +-
 src/mainboard/intel/eagleheights/romstage.c | 2 +-
 src/mainboard/intel/emeraldlake2/romstage.c | 2 +-
 src/mainboard/intel/jarrell/romstage.c      | 2 +-
 src/mainboard/intel/mtarvon/romstage.c      | 2 +-
 src/mainboard/intel/truxton/romstage.c      | 2 +-
 src/mainboard/intel/xe7501devkit/romstage.c | 2 +-
 8 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'src/mainboard/intel')

diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c
index 982060c3b3..8b74b17d9f 100644
--- a/src/mainboard/intel/d810e2cb/romstage.c
+++ b/src/mainboard/intel/d810e2cb/romstage.c
@@ -35,7 +35,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* Set southbridge and Super I/O GPIOs. */
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 94b66104ab..0c48247bda 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -156,7 +156,7 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	u32 reg32;
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 99445b88e5..e35140bfad 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -120,7 +120,7 @@ static void early_config(void)
 	pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	/* int boot_mode = 0; */
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index 12abb548b5..e10e7b62a3 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -162,7 +162,7 @@ static void setup_sio_gpios(void)
 	outb(0xaa, port);
 }
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	int boot_mode = 0;
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index a672afa5b1..f1cf4c3e1f 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -38,7 +38,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "debug.c"
 #include "arch/x86/lib/stages.c"
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	static const struct mem_controller mch[] = {
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index 2e99be558b..c1ee9bb058 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -51,7 +51,7 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "arch/x86/lib/stages.c"
 #endif
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 void main(unsigned long bist)
 {
 	msr_t msr;
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index c56b1dfe31..cd4996758d 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -51,7 +51,7 @@ static inline int spd_read_byte(u16 device, u8 address)
 
 #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
 
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	msr_t msr;
diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
index f35f93ba20..e1a5807f28 100644
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ b/src/mainboard/intel/xe7501devkit/romstage.c
@@ -33,7 +33,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "lib/generic_sdram.c"
 
 // This function MUST appear last (ROMCC limitation)
-#include <cpu/intel/car.h>
+#include <cpu/intel/romstage.h>
 static void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {
-- 
cgit v1.2.3