From bf38d58420340faac5acf595120c6bca35175ffe Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 14 Oct 2020 21:53:59 +0530 Subject: mb/intel/adlrvp: Program GPIO for M.2 PCH SSD This patch programs GPIO for PCH SSD Power Enable (GPP_D16) and Port Detect (GPP_A12) as per schematics. TEST=Able to build and boot ADL RVP. Change-Id: I015e46bdf25437c6b196deb3e610bc1b58726070 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46417 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak --- src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c index 5a2199203f..e142e88e57 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -70,7 +70,11 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_H1, 1, PLTRST), /* Sata direct Power */ PAD_CFG_GPO(GPP_B4, 1, PLTRST), + /* M.2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* THC0 SPI1 CLK */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), /* THC0 SPI1 IO 1 */ -- cgit v1.2.3