From d76d60bf56520ba64898b3fbc4953fc768fef7e8 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Thu, 3 Mar 2016 15:30:48 -0800 Subject: soc/intel/quark: Set the UPD values for MemoryInit Set the UPD values for MemoryInit. * Update the FspUpdVpd.h file which specifies the parameters for MemoryInit. * Add the necessary values to chip.h to enable values to come from the mainboard's devicetree.cb file * Add the parameters to the mainboard's devicetree.cb file * Locate the platform configuration database file (pdat.bin) * Copy the data values from the chip_info structure into the UPDs * Display the UPD values Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_DISPLAY_UPD_DATA=y * Testing successful when the UPD data is displayed before the call to MemoryInit Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/13896 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/mainboard/intel/galileo/devicetree.cb | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/mainboard/intel') diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index 52e019bc9e..c171aa0d6a 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -16,6 +16,16 @@ chip soc/intel/quark + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdSmmTsegSize" = "0" # SMM Region size in MiB + + ############################################################ + # Enable the devices + ############################################################ + device domain 0 on # EDS Table 3 device pci 00.0 on end # 8086 0958 - Host Bridge -- cgit v1.2.3