From 7e577ad22f2f7fb6e2fca062f87c93e1c1dc3344 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 21 May 2020 15:14:07 +0200 Subject: AGESA f14/f15tn/f16kb: Factor out memory settings We use the same values everywhere, so we might as well factor them out. TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries. Change-Id: Ie6f166034d5d642dff37730a8d83264fb2e019b4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/41663 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Krystian Hebel --- src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'src/mainboard/jetway') diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index a20d133f3a..1e81f5b497 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -190,19 +190,6 @@ #define POWER_DOWN_BY_CHANNEL 0 /**< Channel power down mode */ #define POWER_DOWN_BY_CHIP_SELECT 1 /**< Chip select power down mode */ -/** - * The following definitions specify the default values for various parameters - * in which there are no clearly defined defaults to be used in the common - * file. The values below are based on product and BKDG content. - */ -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) - /* AGESA nonsense: this header depends on the definitions above */ /* Instantiate all solution relevant data. */ #include -- cgit v1.2.3