From 38f147ed3d9fdd6bfb23d7226f6fdd3fc5db53d0 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 8 Feb 2010 12:20:50 +0000 Subject: janitor task: unify and cleanup naming. cache_as_ram_auto.c and auto.c are both called "romstage.c" now. Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/kontron/986lcd-m/Makefile.inc | 6 +- src/mainboard/kontron/986lcd-m/auto.c | 488 ------------------------ src/mainboard/kontron/986lcd-m/romstage.c | 488 ++++++++++++++++++++++++ src/mainboard/kontron/kt690/Makefile.inc | 6 +- src/mainboard/kontron/kt690/cache_as_ram_auto.c | 245 ------------ src/mainboard/kontron/kt690/romstage.c | 245 ++++++++++++ 6 files changed, 739 insertions(+), 739 deletions(-) delete mode 100644 src/mainboard/kontron/986lcd-m/auto.c create mode 100644 src/mainboard/kontron/986lcd-m/romstage.c delete mode 100644 src/mainboard/kontron/kt690/cache_as_ram_auto.c create mode 100644 src/mainboard/kontron/kt690/romstage.c (limited to 'src/mainboard/kontron') diff --git a/src/mainboard/kontron/986lcd-m/Makefile.inc b/src/mainboard/kontron/986lcd-m/Makefile.inc index bd0d7b9965..29f43797c0 100644 --- a/src/mainboard/kontron/986lcd-m/Makefile.inc +++ b/src/mainboard/kontron/986lcd-m/Makefile.inc @@ -40,7 +40,7 @@ initobj-y += crt0.o crt0s := $(src)/cpu/x86/32bit/entry32.inc crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc +crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb ldscripts += $(src)/cpu/x86/32bit/entry32.lds @@ -55,8 +55,8 @@ $(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h - $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ +$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@ perl -e 's/\.rodata/.rom.data/g' -pi $@ perl -e 's/\.text/.section .rom.text/g' -pi $@ diff --git a/src/mainboard/kontron/986lcd-m/auto.c b/src/mainboard/kontron/986lcd-m/auto.c deleted file mode 100644 index 29d1d242ff..0000000000 --- a/src/mainboard/kontron/986lcd-m/auto.c +++ /dev/null @@ -1,488 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -// __PRE_RAM__ means: use "unsigned" for device, not a struct. -#define __PRE_RAM__ - -/* Configuration of the i945 driver */ -#define CHIPSET_I945GM 1 -/* Usually system firmware turns off system memory clock signals to - * unused SO-DIMM slots to reduce EMI and power consumption. - * However, the Kontron 986LCD-M does not like unused clock signals to - * be disabled. If other similar mainboard occur, it would make sense - * to make this an entry in the sysinfo structure, and pre-initialize that - * structure in the mainboard's auto.c main() function. For now a - * #define will do. - */ -#define OVERRIDE_CLOCK_DISABLE 1 -#define CHANNEL_XOR_RANDOMIZATION 1 - -#include -#include -#include -#include -#include -#include -#include - -#include "superio/winbond/w83627thg/w83627thg.h" - -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" - -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include - -#if CONFIG_USBDEBUG_DIRECT -#define DBGP_DEFAULT 1 -#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" -#include "pc80/usbdebug_direct_serial.c" -#endif - -#include "lib/ramtest.c" -#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" -#include "superio/winbond/w83627thg/w83627thg_early_serial.c" - -#include "northbridge/intel/i945/udelay.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) - -#include "southbridge/intel/i82801gx/i82801gx.h" -static void setup_ich7_gpios(void) -{ - printk_debug(" GPIOS..."); - /* General Registers */ - outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ - outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ - outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - /* Output Control Registers */ - outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ - /* Input Control Registers */ - outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ - outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ - outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ - outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ -} - -#include "northbridge/intel/i945/early_init.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i945/raminit.h" -#include "northbridge/intel/i945/raminit.c" -#include "northbridge/intel/i945/reset_test.c" -#include "northbridge/intel/i945/errata.c" -#include "northbridge/intel/i945/debug.c" - -static void ich7_enable_lpc(void) -{ - // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); - // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); - // Enable HWM at 0xa00 - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); - // COM3 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); - // COM4 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); - // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); -} - - -/* This box has two superios, so enabling serial becomes slightly excessive. - * We disable a lot of stuff to make sure that there are no conflicts between - * the two. Also set up the GPIOs from the beginning. This is the "no schematic - * but safe anyways" method. - */ -static void early_superio_config_w83627thg(void) -{ - device_t dev; - - dev=PNP_DEV(0x2e, W83627THG_SP1); - pnp_enter_ext_func_mode(dev); - - pnp_write_config(dev, 0x24, 0xc6); // PNPCSV - - pnp_write_config(dev, 0x29, 0x43); // GPIO settings - pnp_write_config(dev, 0x2a, 0x40); // GPIO settings - - dev=PNP_DEV(0x2e, W83627THG_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 4); - pnp_set_enable(dev, 1); - - dev=PNP_DEV(0x2e, W83627THG_SP2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 - pnp_set_enable(dev, 1); - - dev=PNP_DEV(0x2e, W83627THG_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - // pnp_write_config(dev, 0xf0, 0x82); - pnp_set_enable(dev, 1); - - dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs - pnp_set_enable(dev, 1); - - dev=PNP_DEV(0x2e, W83627THG_GPIO2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); // Just enable it - - dev=PNP_DEV(0x2e, W83627THG_GPIO3); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient - - dev=PNP_DEV(0x2e, W83627THG_FDC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev=PNP_DEV(0x2e, W83627THG_PP); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - /* Enable HWM */ - dev=PNP_DEV(0x2e, W83627THG_HWM); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); - pnp_set_enable(dev, 1); - - pnp_exit_ext_func_mode(dev); - - dev=PNP_DEV(0x4e, W83627THG_SP1); - pnp_enter_ext_func_mode(dev); - - pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 11); - pnp_set_enable(dev, 1); - - dev=PNP_DEV(0x4e, W83627THG_SP2); - pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 10); - pnp_set_enable(dev, 1); - - dev=PNP_DEV(0x4e, W83627THG_FDC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev=PNP_DEV(0x4e, W83627THG_PP); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev=PNP_DEV(0x4e, W83627THG_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); - - pnp_exit_ext_func_mode(dev); -} - -static void rcba_config(void) -{ - u32 reg32; - - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; - - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(0x310c) = 0x00214321; - - /* dev irq route register */ - RCBA16(0x3140) = 0x0132; - RCBA16(0x3142) = 0x3241; - RCBA16(0x3144) = 0x0237; - RCBA16(0x3146) = 0x3210; - RCBA16(0x3148) = 0x3210; - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - - /* Enable upper 128bytes of CMOS */ - RCBA32(0x3400) = (1 << 2); - - /* Now, this is a bit ugly. As per PCI specification, function 0 of a - * device always has to be implemented. So disabling ethernet port 1 - * would essentially disable all three ethernet ports of the mainboard. - * It's possible to rename the ports to achieve compatibility to the - * PCI spec but this will confuse all (static!) tables containing - * interrupt routing information. - * To avoid this, we enable (unused) port 6 and swap it with port 1 - * in the case that ethernet port 1 is disabled. Since no devices - * are connected to that port, we don't have to worry about interrupt - * routing. - */ - int port_shuffle = 0; - - /* Disable unused devices */ - reg32 = FD_ACMOD|FD_ACAUD|FD_PATA; - reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4; - - if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) { - printk_debug("Disabling ethernet adapter 1.\n"); - reg32 |= FD_PCIE1; - } - if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) { - printk_debug("Disabling ethernet adapter 2.\n"); - reg32 |= FD_PCIE2; - } else { - if (reg32 & FD_PCIE1) - port_shuffle = 1; - } - if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) { - printk_debug("Disabling ethernet adapter 3.\n"); - reg32 |= FD_PCIE3; - } else { - if (reg32 & FD_PCIE1) - port_shuffle = 1; - } - - if (port_shuffle) { - /* Enable PCIE6 again */ - reg32 &= ~FD_PCIE6; - /* Swap PCIE6 and PCIE1 */ - RCBA32(RPFN) = 0x00043215; - } - - reg32 |= 1; - - RCBA32(0x3418) = reg32; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; -} - -static void early_ich7_init(void) -{ - uint8_t reg8; - uint32_t reg32; - - // program secondary mlt XXX byte? - pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); - - // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); - reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); - - // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); - reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); - reg32 |= (1 << 29) | (1 << 17); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); - - reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); - reg32 |= (1 << 31) | (1 << 27); - pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); - - RCBA32(0x0088) = 0x0011d000; - RCBA16(0x01fc) = 0x060f; - RCBA32(0x01f4) = 0x86000040; - RCBA32(0x0214) = 0x10030549; - RCBA32(0x0218) = 0x00020504; - RCBA8(0x0220) = 0xc5; - reg32 = RCBA32(0x3410); - reg32 |= (1 << 6); - RCBA32(0x3410) = reg32; - reg32 = RCBA32(0x3430); - reg32 &= ~(3 << 0); - reg32 |= (1 << 0); - RCBA32(0x3430) = reg32; - RCBA32(0x3418) |= (1 << 0); - RCBA16(0x0200) = 0x2008; - RCBA8(0x2027) = 0x0d; - RCBA16(0x3e08) |= (1 << 7); - RCBA16(0x3e48) |= (1 << 7); - RCBA32(0x3e0e) |= (1 << 7); - RCBA32(0x3e4e) |= (1 << 7); - - // next step only on ich7m b0 and later: - reg32 = RCBA32(0x2034); - reg32 &= ~(0x0f << 16); - reg32 |= (5 << 16); - RCBA32(0x2034) = reg32; -} - -#if CONFIG_USE_FALLBACK_IMAGE == 1 -#include "southbridge/intel/i82801gx/cmos_failover.c" -#endif - -#include - -// Now, this needs to be included because it relies on the symbol -// __PRE_RAM__ being set during CAR stage (in order to compile the -// BSS free versions of the functions). Either rewrite the code -// to be always BSS free, or invent a flag that's better suited than -// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) -// -#include "lib/cbmem.c" - -void real_main(unsigned long bist) -{ - u32 reg32; - int boot_mode = 0; - - if (bist == 0) { - enable_lapic(); - } - - ich7_enable_lpc(); - early_superio_config_w83627thg(); - - /* Set up the console */ - uart_init(); - -#if CONFIG_USBDEBUG_DIRECT - i82801gx_enable_usbdebug_direct(DBGP_DEFAULT); - early_usbdebug_direct_init(); -#endif - - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - if (MCHBAR16(SSKPD) == 0xCAFE) { - printk_debug("soft reset detected.\n"); - boot_mode = 1; - } - - /* Perform some early chipset initialization required - * before RAM initialization can work - */ - i945_early_initialization(); - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk_debug("PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME - printk_debug("Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - -#else - printk_debug("Resume from S3 detected, but disabled.\n"); -#endif - } - - /* Enable SPD ROMs and DDR-II DRAM */ - enable_smbus(); - -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 - dump_spd_registers(); -#endif - - sdram_initialize(boot_mode); - - /* Perform some initialization that must run before stage2 */ - early_ich7_init(); - - /* This should probably go away. Until now it is required - * and mainboard specific - */ - rcba_config(); - - /* Chipset Errata! */ - fixup_i945_errata(); - - /* Initialize the internal PCIe links before we go into stage2 */ - i945_late_initialization(); - -#if !CONFIG_HAVE_ACPI_RESUME -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 -#if defined(DEBUG_RAM_SETUP) - sdram_dump_mchbar_registers(); -#endif - - { - /* This will not work if TSEG is in place! */ - u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - - printk_debug("TOM: 0x%08x\n", tom); - ram_check(0x00000000, 0x000a0000); - //ram_check(0x00100000, tom); - } -#endif -#endif - - MCHBAR16(SSKPD) = 0xCAFE; - -#if CONFIG_HAVE_ACPI_RESUME - /* Start address of high memory tables */ - unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; - - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - - /* copy 1MB - 64K to high tables ram_base to prevent memory corruption - * through stage 2. We could keep stuff like stack and heap in high tables - * memory completely, but that's a wonderful clean up task for another - * day. - */ - if (resume_backup_memory) - memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } -#endif -} - -#include "cpu/intel/model_6ex/cache_as_ram_disable.c" diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c new file mode 100644 index 0000000000..e0943ab390 --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -0,0 +1,488 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// __PRE_RAM__ means: use "unsigned" for device, not a struct. +#define __PRE_RAM__ + +/* Configuration of the i945 driver */ +#define CHIPSET_I945GM 1 +/* Usually system firmware turns off system memory clock signals to + * unused SO-DIMM slots to reduce EMI and power consumption. + * However, the Kontron 986LCD-M does not like unused clock signals to + * be disabled. If other similar mainboard occur, it would make sense + * to make this an entry in the sysinfo structure, and pre-initialize that + * structure in the mainboard's romstage.c main() function. For now a + * #define will do. + */ +#define OVERRIDE_CLOCK_DISABLE 1 +#define CHANNEL_XOR_RANDOMIZATION 1 + +#include +#include +#include +#include +#include +#include +#include + +#include "superio/winbond/w83627thg/w83627thg.h" + +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" + +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include + +#if CONFIG_USBDEBUG_DIRECT +#define DBGP_DEFAULT 1 +#include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" +#include "pc80/usbdebug_direct_serial.c" +#endif + +#include "lib/ramtest.c" +#include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" +#include "superio/winbond/w83627thg/w83627thg_early_serial.c" + +#include "northbridge/intel/i945/udelay.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + +#include "southbridge/intel/i82801gx/i82801gx.h" +static void setup_ich7_gpios(void) +{ + printk_debug(" GPIOS..."); + /* General Registers */ + outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ +} + +#include "northbridge/intel/i945/early_init.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i945/raminit.h" +#include "northbridge/intel/i945/raminit.c" +#include "northbridge/intel/i945/reset_test.c" +#include "northbridge/intel/i945/errata.c" +#include "northbridge/intel/i945/debug.c" + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); + // Set COM1/COM2 decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + // Enable COM1/COM2/KBD/SuperIO1+2 + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); + // Enable HWM at 0xa00 + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); + // COM3 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); + // COM4 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); + // io 0x300 decode + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); +} + + +/* This box has two superios, so enabling serial becomes slightly excessive. + * We disable a lot of stuff to make sure that there are no conflicts between + * the two. Also set up the GPIOs from the beginning. This is the "no schematic + * but safe anyways" method. + */ +static void early_superio_config_w83627thg(void) +{ + device_t dev; + + dev=PNP_DEV(0x2e, W83627THG_SP1); + pnp_enter_ext_func_mode(dev); + + pnp_write_config(dev, 0x24, 0xc6); // PNPCSV + + pnp_write_config(dev, 0x29, 0x43); // GPIO settings + pnp_write_config(dev, 0x2a, 0x40); // GPIO settings + + dev=PNP_DEV(0x2e, W83627THG_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_SP2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + // pnp_write_config(dev, 0xf1, 4); // IRMODE0 + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + // pnp_write_config(dev, 0xf0, 0x82); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627THG_GPIO2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); // Just enable it + + dev=PNP_DEV(0x2e, W83627THG_GPIO3); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output + pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 + pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + + dev=PNP_DEV(0x2e, W83627THG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x2e, W83627THG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + /* Enable HWM */ + dev=PNP_DEV(0x2e, W83627THG_HWM); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); + pnp_set_enable(dev, 1); + + pnp_exit_ext_func_mode(dev); + + dev=PNP_DEV(0x4e, W83627THG_SP1); + pnp_enter_ext_func_mode(dev); + + pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 11); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x4e, W83627THG_SP2); + pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 10); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x4e, W83627THG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x4e, W83627THG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x4e, W83627THG_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); + + pnp_exit_ext_func_mode(dev); +} + +static void rcba_config(void) +{ + u32 reg32; + + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + //RCBA32(0x001c) = 0x03128010; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x3241; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3210; + RCBA16(0x3148) = 0x3210; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Now, this is a bit ugly. As per PCI specification, function 0 of a + * device always has to be implemented. So disabling ethernet port 1 + * would essentially disable all three ethernet ports of the mainboard. + * It's possible to rename the ports to achieve compatibility to the + * PCI spec but this will confuse all (static!) tables containing + * interrupt routing information. + * To avoid this, we enable (unused) port 6 and swap it with port 1 + * in the case that ethernet port 1 is disabled. Since no devices + * are connected to that port, we don't have to worry about interrupt + * routing. + */ + int port_shuffle = 0; + + /* Disable unused devices */ + reg32 = FD_ACMOD|FD_ACAUD|FD_PATA; + reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4; + + if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) { + printk_debug("Disabling ethernet adapter 1.\n"); + reg32 |= FD_PCIE1; + } + if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) { + printk_debug("Disabling ethernet adapter 2.\n"); + reg32 |= FD_PCIE2; + } else { + if (reg32 & FD_PCIE1) + port_shuffle = 1; + } + if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) { + printk_debug("Disabling ethernet adapter 3.\n"); + reg32 |= FD_PCIE3; + } else { + if (reg32 & FD_PCIE1) + port_shuffle = 1; + } + + if (port_shuffle) { + /* Enable PCIE6 again */ + reg32 &= ~FD_PCIE6; + /* Swap PCIE6 and PCIE1 */ + RCBA32(RPFN) = 0x00043215; + } + + reg32 |= 1; + + RCBA32(0x3418) = reg32; + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + + // program secondary mlt XXX byte? + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); + + // reset rtc power status + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + + // usb transient disconnect + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); + RCBA32(0x3e0e) |= (1 << 7); + RCBA32(0x3e4e) |= (1 << 7); + + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; +} + +#if CONFIG_USE_FALLBACK_IMAGE == 1 +#include "southbridge/intel/i82801gx/cmos_failover.c" +#endif + +#include + +// Now, this needs to be included because it relies on the symbol +// __PRE_RAM__ being set during CAR stage (in order to compile the +// BSS free versions of the functions). Either rewrite the code +// to be always BSS free, or invent a flag that's better suited than +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) +// +#include "lib/cbmem.c" + +void real_main(unsigned long bist) +{ + u32 reg32; + int boot_mode = 0; + + if (bist == 0) { + enable_lapic(); + } + + ich7_enable_lpc(); + early_superio_config_w83627thg(); + + /* Set up the console */ + uart_init(); + +#if CONFIG_USBDEBUG_DIRECT + i82801gx_enable_usbdebug_direct(DBGP_DEFAULT); + early_usbdebug_direct_init(); +#endif + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk_debug("soft reset detected.\n"); + boot_mode = 1; + } + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i945_early_initialization(); + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk_debug("PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk_debug("Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + +#else + printk_debug("Resume from S3 detected, but disabled.\n"); +#endif + } + + /* Enable SPD ROMs and DDR-II DRAM */ + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + + sdram_initialize(boot_mode); + + /* Perform some initialization that must run before stage2 */ + early_ich7_init(); + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + /* Chipset Errata! */ + fixup_i945_errata(); + + /* Initialize the internal PCIe links before we go into stage2 */ + i945_late_initialization(); + +#if !CONFIG_HAVE_ACPI_RESUME +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +#if defined(DEBUG_RAM_SETUP) + sdram_dump_mchbar_registers(); +#endif + + { + /* This will not work if TSEG is in place! */ + u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + + printk_debug("TOM: 0x%08x\n", tom); + ram_check(0x00000000, 0x000a0000); + //ram_check(0x00100000, tom); + } +#endif +#endif + + MCHBAR16(SSKPD) = 0xCAFE; + +#if CONFIG_HAVE_ACPI_RESUME + /* Start address of high memory tables */ + unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; + + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } +#endif +} + +#include "cpu/intel/model_6ex/cache_as_ram_disable.c" diff --git a/src/mainboard/kontron/kt690/Makefile.inc b/src/mainboard/kontron/kt690/Makefile.inc index dda9ecf044..482dfff724 100644 --- a/src/mainboard/kontron/kt690/Makefile.inc +++ b/src/mainboard/kontron/kt690/Makefile.inc @@ -38,7 +38,7 @@ crt0s += $(src)/cpu/x86/32bit/entry32.inc crt0s += $(src)/cpu/x86/16bit/reset16.inc crt0s += $(src)/arch/i386/lib/id.inc crt0s += $(src)/cpu/amd/car/cache_as_ram.inc -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc +crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb ldscripts += $(src)/cpu/x86/16bit/entry16.lds @@ -55,8 +55,8 @@ $(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/acpi/dsdt.asl $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ -$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h - $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ +$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@ perl -e 's/\.rodata/.rom.data/g' -pi $@ perl -e 's/\.text/.section .rom.text/g' -pi $@ diff --git a/src/mainboard/kontron/kt690/cache_as_ram_auto.c b/src/mainboard/kontron/kt690/cache_as_ram_auto.c deleted file mode 100644 index 224f60365d..0000000000 --- a/src/mainboard/kontron/kt690/cache_as_ram_auto.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#define RAMINIT_SYSINFO 1 -#define K8_SET_FIDVID 1 -#define QRANK_DIMM_SUPPORT 1 -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - -#define RC0 (6<<8) -#define RC1 (7<<8) - -#define DIMM0 0x50 -#define DIMM1 0x51 - -#define ICS951462_ADDRESS 0x69 -#define SMBUS_HUB 0x71 - -#include -#include -#include -#include -#include -#include -#include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" - -#define post_code(x) outb(x, 0x80) - -#include -#include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" - -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" - -#include "cpu/amd/mtrr/amd_earlymtrr.c" -#include "cpu/x86/bist.h" - -#include "northbridge/amd/amdk8/setup_resource_map.c" - -#include "southbridge/amd/rs690/rs690_early_setup.c" -#include "southbridge/amd/sb600/sb600_early_setup.c" - -/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -/* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} - -/*called in raminit_f.c */ -static inline int spd_read_byte(u32 device, u32 address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/amd/amdk8/amdk8.h" -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" -#include "resourcemap.c" - -#include "cpu/amd/dualcore/dualcore.c" - -#include "cpu/amd/car/copy_and_run.c" -#include "cpu/amd/car/post_cache_as_ram.c" - -#include "cpu/amd/model_fxx/init_cpus.c" - -#include "cpu/amd/model_fxx/fidvid.c" - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - -#include "northbridge/amd/amdk8/early_ht.c" - -void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) -{ - /* Is this a cpu only reset? Is this a secondary cpu? */ - if ((cpu_init_detectedx) || (!boot_cpu())) { - if (last_boot_normal()) { /* RTC already inited */ - goto normal_image; - } else { - goto fallback_image; - } - } - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* sb600_lpc_port80(); */ - sb600_pci_port80(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } else { - goto fallback_image; - } -normal_image: - post_code(0x23); - __asm__ volatile ("jmp __normal_image": /* outputs */ - :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); - -fallback_image: - post_code(0x25); -} -#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - -#if CONFIG_USE_FALLBACK_IMAGE == 1 - failover_process(bist, cpu_init_detectedx); -#endif - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ - device_t dev; - static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; - int needs_reset = 0; - u32 bsp_apicid = 0; - msr_t msr; - struct cpuid_result cpuid1; - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } - - enable_rs690_dev8(); - sb600_lpc_init(); - - dev=PNP_DEV(0x2e, W83627DHG_SP1); - w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - printk_debug("bsp_apicid=0x%x\n", bsp_apicid); - - setup_kt690_resource_map(); - - setup_coherent_ht_domain(); - -#if CONFIG_LOGICAL_CPUS==1 - /* It is said that we should start core1 after all core0 launched */ - wait_all_core0_started(); - start_other_cores(); -#endif - wait_all_aps_started(bsp_apicid); - - ht_setup_chains_x(sysinfo); - - /* run _early_setup before soft-reset. */ - rs690_early_setup(); - sb600_early_setup(); - - /* Check to see if processor is capable of changing FIDVID */ - /* otherwise it will throw a GP# when reading FIDVID_STATUS */ - cpuid1 = cpuid(0x80000007); - if( (cpuid1.edx & 0x6) == 0x6 ) { - - /* Read FIDVID_STATUS */ - msr=rdmsr(0xc0010042); - printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - - /* show final fid and vid */ - msr=rdmsr(0xc0010042); - printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - - } else { - printk_debug("Changing FIDVID not supported\n"); - printk_spew("... because cpuid returned %08x\n", cpuid1.edx); - } - - needs_reset = optimize_link_coherent_ht(); - needs_reset |= optimize_link_incoherent_ht(sysinfo); - rs690_htinit(); - printk_debug("needs_reset=0x%x\n", needs_reset); - - - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } - - allow_all_aps_stop(bsp_apicid); - - /* It's the time to set ctrl now; */ - printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n", - sysinfo->nodes, sysinfo->ctrl, spd_addr); - fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - - rs690_before_pci_init(); - sb600_before_pci_init(); - - post_cache_as_ram(); -} diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c new file mode 100644 index 0000000000..224f60365d --- /dev/null +++ b/src/mainboard/kontron/kt690/romstage.c @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __PRE_RAM__ + +#define RAMINIT_SYSINFO 1 +#define K8_SET_FIDVID 1 +#define QRANK_DIMM_SUPPORT 1 +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif + +#define RC0 (6<<8) +#define RC1 (7<<8) + +#define DIMM0 0x50 +#define DIMM1 0x51 + +#define ICS951462_ADDRESS 0x69 +#define SMBUS_HUB 0x71 + +#include +#include +#include +#include +#include +#include +#include +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" + +#define post_code(x) outb(x, 0x80) + +#include +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#include "southbridge/amd/rs690/rs690_early_setup.c" +#include "southbridge/amd/sb600/sb600_early_setup.c" + +/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +/* called in raminit_f.c */ +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +/*called in raminit_f.c */ +static inline int spd_read_byte(u32 device, u32 address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/raminit_f.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "lib/generic_sdram.c" +#include "resourcemap.c" + +#include "cpu/amd/dualcore/dualcore.c" + +#include "cpu/amd/car/copy_and_run.c" +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + +#include "cpu/amd/model_fxx/fidvid.c" + +#if CONFIG_USE_FALLBACK_IMAGE == 1 + +#include "northbridge/amd/amdk8/early_ht.c" + +void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) +{ + /* Is this a cpu only reset? Is this a secondary cpu? */ + if ((cpu_init_detectedx) || (!boot_cpu())) { + if (last_boot_normal()) { /* RTC already inited */ + goto normal_image; + } else { + goto fallback_image; + } + } + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } else { + goto fallback_image; + } +normal_image: + post_code(0x23); + __asm__ volatile ("jmp __normal_image": /* outputs */ + :"a" (bist), "b"(cpu_init_detectedx) /* inputs */); + +fallback_image: + post_code(0x25); +} +#endif /* CONFIG_USE_FALLBACK_IMAGE == 1 */ + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx); + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + +#if CONFIG_USE_FALLBACK_IMAGE == 1 + failover_process(bist, cpu_init_detectedx); +#endif + real_main(bist, cpu_init_detectedx); +} + +void real_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + device_t dev; + static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; + int needs_reset = 0; + u32 bsp_apicid = 0; + msr_t msr; + struct cpuid_result cpuid1; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } + + enable_rs690_dev8(); + sb600_lpc_init(); + + dev=PNP_DEV(0x2e, W83627DHG_SP1); + w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + printk_debug("bsp_apicid=0x%x\n", bsp_apicid); + + setup_kt690_resource_map(); + + setup_coherent_ht_domain(); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched */ + wait_all_core0_started(); + start_other_cores(); +#endif + wait_all_aps_started(bsp_apicid); + + ht_setup_chains_x(sysinfo); + + /* run _early_setup before soft-reset. */ + rs690_early_setup(); + sb600_early_setup(); + + /* Check to see if processor is capable of changing FIDVID */ + /* otherwise it will throw a GP# when reading FIDVID_STATUS */ + cpuid1 = cpuid(0x80000007); + if( (cpuid1.edx & 0x6) == 0x6 ) { + + /* Read FIDVID_STATUS */ + msr=rdmsr(0xc0010042); + printk_debug("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + + /* show final fid and vid */ + msr=rdmsr(0xc0010042); + printk_debug("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + } else { + printk_debug("Changing FIDVID not supported\n"); + printk_spew("... because cpuid returned %08x\n", cpuid1.edx); + } + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs690_htinit(); + printk_debug("needs_reset=0x%x\n", needs_reset); + + + if (needs_reset) { + print_info("ht reset -\r\n"); + soft_reset(); + } + + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now; */ + printk_debug("sysinfo->nodes: %2x sysinfo->ctrl: %2x spd_addr: %2x\n", + sysinfo->nodes, sysinfo->ctrl, spd_addr); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + + rs690_before_pci_init(); + sb600_before_pci_init(); + + post_cache_as_ram(); +} -- cgit v1.2.3