From abf2ad716daff751d75907d47bcae4a7044fd7b4 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sun, 7 Feb 2010 21:43:48 +0000 Subject: newconfig is no more. Signed-off-by: Patrick Georgi Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/kontron/986lcd-m/Config.lb | 270 ------------------------ src/mainboard/kontron/986lcd-m/Options.lb | 328 ------------------------------ src/mainboard/kontron/kt690/Config.lb | 262 ------------------------ src/mainboard/kontron/kt690/Options.lb | 301 --------------------------- 4 files changed, 1161 deletions(-) delete mode 100644 src/mainboard/kontron/986lcd-m/Config.lb delete mode 100644 src/mainboard/kontron/986lcd-m/Options.lb delete mode 100644 src/mainboard/kontron/kt690/Config.lb delete mode 100644 src/mainboard/kontron/kt690/Options.lb (limited to 'src/mainboard/kontron') diff --git a/src/mainboard/kontron/986lcd-m/Config.lb b/src/mainboard/kontron/986lcd-m/Config.lb deleted file mode 100644 index 66ada57c65..0000000000 --- a/src/mainboard/kontron/986lcd-m/Config.lb +++ /dev/null @@ -1,270 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## - -## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - -## -## Only use the option table in a normal image -## -default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE - -## -## Image size calculation -## - -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o -driver rtl8168.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -if CONFIG_HAVE_SMI_HANDLER smmobject mainboard_smi.o end - -if CONFIG_GENERATE_ACPI_TABLES - object fadt.o - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "$(CONFIG_CROSS_COMPILE)cpp -D__ACPI__ -P $(CPPFLAGS) -I$(CONFIG_MAINBOARD) $(CONFIG_MAINBOARD)/dsdt.asl -o $(CURDIR)/dsdt.asl" - action "iasl -p dsdt -tc $(CURDIR)/dsdt.asl" - action "mv $(CURDIR)/dsdt.hex dsdt.c" - end - object ./dsdt.o -end - -if CONFIG_USE_INIT - -makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -else - -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" -end - -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - ldscript /cpu/x86/car/cache_as_ram.lds -end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -## -## Setup Cache-As-Ram -## -mainboardinit cpu/intel/model_6ex/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -if CONFIG_USE_INIT -initobject auto.o -else -mainboardinit ./auto.inc -end - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/i945 - - device apic_cluster 0 on - chip cpu/intel/socket_mFCPGA478 - device apic 0 on end - end - end - - device pci_domain 0 on - device pci 00.0 on end # host bridge - # autodetect 0:1.0 because it might or might not be there. - # device pci 01.0 off end # i945 PCIe root port - device pci 02.0 on end # vga controller - device pci 02.1 on end # display controller - - chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x05" - register "pirqb_routing" = "0x07" - register "pirqc_routing" = "0x05" - register "pirqd_routing" = "0x07" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x06" - - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "1" - register "gpe0_en" = "0x00000400" - - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x1" - register "sata_ahci" = "0x0" - - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe - device pci 1c.1 on end # PCIe - device pci 1c.2 on end # PCIe - #device pci 1c.3 off end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 - device pci 1d.0 on end # USB UHCI - device pci 1d.1 on end # USB UHCI - device pci 1d.2 on end # USB UHCI - device pci 1d.3 on end # USB UHCI - device pci 1d.7 on end # USB2 EHCI - device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio - #device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # LPC bridge - chip superio/winbond/w83627thg - device pnp 2e.0 off # Floppy - end - device pnp 2e.1 off # Parport - end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq - end - device pnp 2e.5 on # Keyboard+Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - irq 0xf0 = 0x82 # HW accel A20. - end - device pnp 2e.7 on # GPIO1, GAME, MIDI - io 0x62 = 0x330 - irq 0x70 = 9 - end - device pnp 2e.8 on # GPIO2 - # all default - end - device pnp 2e.9 on # GPIO3/4 - irq 0x30 = 0x03 # does this work? - irq 0xf0 = 0xfb # set inputs/outputs - irq 0xf1 = 0x66 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # HWM - io 0x60 = 0xa00 - irq 0x70 = 0 - end - - end - chip superio/winbond/w83627thg - device pnp 4e.0 off # Floppy - end - device pnp 4e.1 off # Parport - end - device pnp 4e.2 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 11 - end - device pnp 4e.3 on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 10 - end - device pnp 4e.5 off # Keyboard - end - device pnp 4e.7 off # GPIO1, GAME, MIDI - end - device pnp 4e.8 off # GPIO2 - end - device pnp 4e.9 off # GPIO3/4 - end - device pnp 4e.a off # ACPI - end - device pnp 4e.b off # HWM - end - end - - end - #device pci 1f.1 off end # IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - #device pci 1f.4 off end # Realtek ID Codec - end - end -end diff --git a/src/mainboard/kontron/986lcd-m/Options.lb b/src/mainboard/kontron/986lcd-m/Options.lb deleted file mode 100644 index 811d8efdb3..0000000000 --- a/src/mainboard/kontron/986lcd-m/Options.lb +++ /dev/null @@ -1,328 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -## MA 02110-1301 USA -## - -# Tables -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_HAVE_MAINBOARD_RESOURCES -# SMP -uses CONFIG_SMP -uses CONFIG_LOGICAL_CPUS -uses CONFIG_AP_IN_SIPI_WAIT -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_IOAPIC -# Image Size -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -# Payload -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -# Build Internals -uses CONFIG_RAMBASE -uses CONFIG_ROMBASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_XIP_ROM_BASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_SMI_HANDLER -uses CONFIG_PCIE_CONFIGSPACE_HOLE -uses CONFIG_MMCONF_SUPPORT -uses CONFIG_MMCONF_BASE_ADDRESS -uses CONFIG_GFXUMA - -# -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -# Timers -uses CONFIG_UDELAY_LAPIC -# Console -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_VGA -uses CONFIG_VGA_ROM_RUN -uses CONFIG_PCI_ROM_RUN -uses CONFIG_DEBUG -# Toolchain -uses CC -uses HOSTCC -uses CONFIG_CROSS_COMPILE -uses CONFIG_OBJCOPY -# Tweaks -uses CONFIG_GDB_STUB -uses CONFIG_MAX_REBOOT_CNT -uses CONFIG_USE_WATCHDOG_ON_BOOT -uses COREBOOT_EXTRA_VERSION -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL - -### -### Build options -### - -## -## -default CONFIG_MAX_REBOOT_CNT=3 - -## -## Use the watchdog to break out of a lockup condition -## -default CONFIG_USE_WATCHDOG_ON_BOOT=0 - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=1024*1024 - - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Delay timer options -## -default CONFIG_UDELAY_LAPIC=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build SMI handler -## -default CONFIG_HAVE_SMI_HANDLER=1 - -## -## Leave a hole for mmapped PCIe config space -## - -default CONFIG_PCIE_CONFIGSPACE_HOLE=1 -default CONFIG_MMCONF_SUPPORT=1 -default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 - -## -## UMA -## -default CONFIG_GFXUMA=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=18 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## -## Build code to provide ACPI support -## -default CONFIG_GENERATE_ACPI_TABLES=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 -default CONFIG_HAVE_ACPI_RESUME=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=1 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -# There are some network option roms that don't work with -# coreboot's x86emu. Thus, we only execute the VGA option rom -# for now: -default CONFIG_VGA_ROM_RUN=1 -default CONFIG_PCI_ROM_RUN=0 -default CONFIG_DEBUG=0 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=4 -default CONFIG_MAX_PHYSICAL_CPUS=2 -default CONFIG_LOGICAL_CPUS=1 -default CONFIG_AP_IN_SIPI_WAIT=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024) -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## Execute In Place settings -## - -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE ) - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="986LCD-M" -default CONFIG_MAINBOARD_VENDOR= "KONTRON" - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 0x10000 - -## -## Use a small 32K stack -## -default CONFIG_STACK_SIZE=0x8000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - - -### -### Compute the location and size of where this firmware image -### (coreboot plus bootloader) will live in the boot rom chip. -### -default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD=1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -### End Options.lb -end diff --git a/src/mainboard/kontron/kt690/Config.lb b/src/mainboard/kontron/kt690/Config.lb deleted file mode 100644 index 3cddb5166e..0000000000 --- a/src/mainboard/kontron/kt690/Config.lb +++ /dev/null @@ -1,262 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -#dir /drivers/si/3114 - -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE - object get_bus_conf.o - object irq_tables.o -end - -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - object fadt.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/acpi/*.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end - - if CONFIG_USE_INIT - - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - - else - - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - - end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - - ## - ## Setup Cache-As-Ram - ## - mainboardinit cpu/amd/car/cache_as_ram.inc - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -## -## Include the secondary Configuration files -## -config chip.h - -#The variables belong to mainboard are defined here. - -#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) -#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) -#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, -# 1: the system allows a PCIE link to be established on Dev2 or Dev3. -#Define gfx_dual_slot, 0: single slot, 1: dual slot -#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable -#Define gfx_tmds, 0: didn't support TMDS, 1: support -#Define gfx_compliance, 0: didn't support compliance, 1: support -#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration -#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_S1G1 - device apic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/winbond/w83627dhg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - #device pnp 2e.6 off # SPI - #end - device pnp 2e.7 off # GPIO - end - device pnp 2e.8 on # WDTO#, PLED - end - device pnp 2e.9 off # GPIO - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # HWM - io 0x60 = 0xa10 - end - device pnp 2e.c off # PECI, SST - end - end #superio/winbond/w83627dhg - #chip superio/smsc/fdc37n972 - # seems this chip is not used? - #end - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "hda_viddid" = "0x10ec0888" - end #southbridge/amd/sb600 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #pci_domain -end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/kontron/kt690/Options.lb b/src/mainboard/kontron/kt690/Options.lb deleted file mode 100644 index 6e3ad131eb..0000000000 --- a/src/mainboard/kontron/kt690/Options.lb +++ /dev/null @@ -1,301 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Advanced Micro Devices, Inc. -## Copyright (C) 2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## -## -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 - -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT - -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_USE_PRINTK_IN_CAR - -uses CONFIG_VIDEO_MB -uses CONFIG_GFXUMA -uses CONFIG_HAVE_MAINBOARD_RESOURCES - -### -### Build options -### - -## -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -## -default CONFIG_ROM_SIZE=524288 - -## -## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use -## -#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -#256K -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT=1 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE=1 -default CONFIG_IRQ_SLOT_COUNT=11 - -## -## Build code to export an x86 MP table -## Useful for specifying IRQ routing values -## -default CONFIG_GENERATE_MP_TABLE=1 - -## ACPI tables will be included -default CONFIG_GENERATE_ACPI_TABLES=1 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE=0 - -## -## Move the default coreboot cmos range off of AMD RTC registers -## -default CONFIG_LB_CKS_RANGE_START=49 -default CONFIG_LB_CKS_RANGE_END=122 -default CONFIG_LB_CKS_LOC=123 - -## -## Build code for SMP support -## Only worry about 2 micro processors -## -default CONFIG_SMP=1 -default CONFIG_MAX_CPUS=2 - -default CONFIG_MAX_PHYSICAL_CPUS=1 -default CONFIG_LOGICAL_CPUS=1 - -#1G memory hole -default CONFIG_HW_MEM_HOLE_SIZEK=0x100000 - -#VGA Console -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - -# BTDC: Only one HT device on Herring. -#HT Unit ID offset -#default CONFIG_HT_CHAIN_UNITID_BASE=0x6 -default CONFIG_HT_CHAIN_UNITID_BASE=0x0 - - -#real SB Unit ID -default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1 - -#make the SB HT chain on bus 0 -default CONFIG_SB_HT_CHAIN_ON_BUS0=1 - -## -## enable CACHE_AS_RAM specifics -## -default CONFIG_USE_DCACHE_RAM=1 -default CONFIG_DCACHE_RAM_BASE=0xc8000 -default CONFIG_DCACHE_RAM_SIZE=0x8000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 -default CONFIG_USE_INIT=0 - -## -## Build code to setup a generic IOAPIC -## -default CONFIG_IOAPIC=1 - -## -## Clean up the motherboard id strings -## -default CONFIG_MAINBOARD_PART_NUMBER="KT690" -default CONFIG_MAINBOARD_VENDOR="KONTRON" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1488 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x6900 - - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 - -## -## Use a small 32K stack -## -default CONFIG_STACK_SIZE=0x8000 - -## -## Use a small 32K heap -## -default CONFIG_HEAP_SIZE=0x8000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -## -## coreboot C code runs at this location in RAM -## -default CONFIG_RAMBASE=0x00100000 - -## -## Load the payload from the ROM -## -default CONFIG_ROM_PAYLOAD = 1 - -### -### Defaults of options that you may want to override in the target config file -### - -## -## The default compiler -## -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## Disable the gdb stub by default -## -default CONFIG_GDB_STUB=0 - - -default CONFIG_USE_PRINTK_IN_CAR=1 - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 - -## -## Select power on after power fail setting -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON" - -default CONFIG_VIDEO_MB=1 -default CONFIG_GFXUMA=1 -default CONFIG_HAVE_MAINBOARD_RESOURCES=1 - -end -- cgit v1.2.3