From ad787e18e0ed24495132d0e9e638ed835afad354 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 30 Sep 2019 04:14:19 +0300 Subject: intel/i945,i82801gx: Refactor early PCI bridge reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/kontron/986lcd-m/romstage.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'src/mainboard/kontron') diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index cee7c2a603..c0e6071301 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include @@ -246,10 +245,8 @@ void mainboard_romstage_entry(void) enable_lapic(); - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); + /* Force PCIRST# to conventional PCI slot and Firewire. */ + ich7_p2p_secondary_reset(); ich7_enable_lpc(); early_superio_config_w83627thg(); -- cgit v1.2.3