From fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 19:11:50 +0100 Subject: nb/intel/sandybridge: Set up console in bootblock Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/lenovo/s230u/Makefile.inc | 2 + src/mainboard/lenovo/s230u/early_init.c | 102 ++++++++++++++++++++++++++++++ src/mainboard/lenovo/s230u/romstage.c | 106 -------------------------------- 3 files changed, 104 insertions(+), 106 deletions(-) create mode 100644 src/mainboard/lenovo/s230u/early_init.c delete mode 100644 src/mainboard/lenovo/s230u/romstage.c (limited to 'src/mainboard/lenovo/s230u') diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index aa4c4f879d..12e77097e4 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -16,3 +16,5 @@ SPD_SOURCES += samsung_2gb # 0b0111 SPD_SOURCES += hynix_2gb # 0b1000 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c new file mode 100644 index 0000000000..6bc92b2cac --- /dev/null +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ec.h" + +#define SPD_LEN 256 + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + + /* Memory map KB9012 EC registers */ + pci_write_config32( + PCH_LPC_DEV, LGMR, + CONFIG_EC_BASE_ADDRESS | 1); + pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); + + /* Enable external USB port power. */ + if (CONFIG(USBDEBUG)) + ec_mm_set_bit(0x3b, 4); +} + +void mainboard_late_rcba_config(void) +{ + /* Disable devices. */ + RCBA32(BUC) = 0x00000020; +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 0, 1 }, + { 1, 1, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 0, 1, 3 }, + { 1, 0, 4 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 1, 6 }, + { 1, 1, 6 }, +}; + +static const char *mainboard_spd_names[9] = { + "ELPIDA 4GB", + "SAMSUNG 4GB", + "HYNIX 4GB", + "ELPIDA 8GB", + "SAMSUNG 8GB", + "HYNIX 8GB", + "ELPIDA 2GB", + "SAMSUNG 2GB", + "HYNIX 2GB", +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + const int spd_gpios[] = {71, 70, 16, 48, -1}; + + u32 spd_index = get_gpios(spd_gpios); + if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) { + /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */ + spd_index = 6; + } + + printk(BIOS_INFO, "SPD index %d (%s)\n", + spd_index, mainboard_spd_names[spd_index]); + + /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + + if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) + die("SPD data not found."); + + memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN); +} diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c deleted file mode 100644 index 0552170668..0000000000 --- a/src/mainboard/lenovo/s230u/romstage.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Tobias Diedrich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ec.h" - -#define SPD_LEN 256 - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); - - /* Memory map KB9012 EC registers */ - pci_write_config32( - PCH_LPC_DEV, LGMR, - CONFIG_EC_BASE_ADDRESS | 1); - pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); - - /* Enable external USB port power. */ - if (CONFIG(USBDEBUG)) - ec_mm_set_bit(0x3b, 4); -} - -void mainboard_late_rcba_config(void) -{ - /* Disable devices. */ - RCBA32(BUC) = 0x00000020; -} -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 0, 1 }, - { 1, 1, 2 }, - { 1, 0, 2 }, - { 0, 0, 3 }, - { 0, 1, 3 }, - { 1, 0, 4 }, - { 1, 1, 4 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 1, 6 }, -}; - -void mainboard_config_superio(void) -{ -} - -static const char *mainboard_spd_names[9] = { - "ELPIDA 4GB", - "SAMSUNG 4GB", - "HYNIX 4GB", - "ELPIDA 8GB", - "SAMSUNG 8GB", - "HYNIX 8GB", - "ELPIDA 2GB", - "SAMSUNG 2GB", - "HYNIX 2GB", -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - void *spd_file; - size_t spd_file_len = 0; - const int spd_gpios[] = {71, 70, 16, 48, -1}; - - u32 spd_index = get_gpios(spd_gpios); - if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) { - /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */ - spd_index = 6; - } - - printk(BIOS_INFO, "SPD index %d (%s)\n", - spd_index, mainboard_spd_names[spd_index]); - - /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - - if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) - die("SPD data not found."); - - memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN); -} -- cgit v1.2.3